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Merge pull request #5388 from jix/bufnorm-followup

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Refactor and fixes to incremental bufNormalize + related changes
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Jannis Harder 2025-09-29 15:15:29 +02:00 • committed by GitHub
commit 47639f8a98
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6 changed files with 292 additions and 120 deletions
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3
passes/cmds/portarcs.cc
View file

@ -124,7 +124,8 @@ struct PortarcsPass : Pass {
TopoSort<SigBit> sort;
for (auto cell : m->cells())
if (cell->type != ID($buf)) {
// Ignore all bufnorm helper cells
if (!cell->type.in(ID($buf), ID($input_port), ID($connect))) {
auto tdata = tinfo.find(cell->type);
if (tdata == tinfo.end())
log_cmd_error("Missing timing data for module '%s'.\n", log_id(cell->type));

14
passes/opt/opt_clean.cc
View file

@ -635,9 +635,17 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
}
}
for (auto cell : delcells) {
if (verbose)
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
if (verbose) {
if (cell->type == ID($connect))
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
else if (cell->type == ID($input_port))
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
else
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
}
module->remove(cell);
}
if (!delcells.empty())