842 commits

Author	SHA1	Message	Date
Eddie Hung	a2ef93f03a	abc -> abc9	2019-10-04 17:56:38 -07:00
Eddie Hung	a5ac33f230	Merge branch 'master' into eddie/abc_to_abc9	2019-10-04 17:53:20 -07:00
Eddie Hung	bbc0e06af3	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-10-04 17:39:08 -07:00
Eddie Hung	0acc51c3d8	Add temporary abc9 -nomfs and use for synth_xilinx -abc9	2019-10-04 17:35:43 -07:00
Eddie Hung	d4212d128b	Use read_args for read_verilog	2019-10-04 17:27:05 -07:00
Eddie Hung	9c23811839	Remove DSP48E1 from *_cells_xtra.v	2019-10-04 17:26:42 -07:00
Eddie Hung	7959e9d6b2	Fix merge issues	2019-10-04 17:21:14 -07:00
Eddie Hung	7a45cd5856	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
Eddie Hung	aae2b9fd9c	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
Eddie Hung	655f1b2ac5	English	2019-10-03 10:11:25 -07:00
Eddie Hung	5299884f04	More fixes	2019-10-01 13:41:08 -07:00
Eddie Hung	03ebe43e3e	Escape Verilog identifiers for legality outside of Yosys	2019-10-01 13:05:56 -07:00
Eddie Hung	e529872b01	Remove need for $currQ port connection	2019-09-30 16:33:40 -07:00
Eddie Hung	5e9ae90cbb	Add explanation to abc_map.v	2019-09-30 15:39:24 -07:00
Eddie Hung	8684b58bed	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-30 12:29:35 -07:00
Eddie Hung	5b5756b91e	Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}	2019-09-30 12:52:43 +02:00
Marcin Kościelnicki	4535f2c694	synth_xilinx: Support latches, remove used-up FF init values. ... Fixes #1387.	2019-09-30 12:52:43 +02:00
Eddie Hung	f6203e6bd6	Missing endmodule	2019-09-29 21:55:53 -07:00
Eddie Hung	1123c09588	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-29 19:39:12 -07:00
Eddie Hung	8474c5b366	Merge pull request #1359 from YosysHQ/xc7dsp ... DSP inference for Xilinx (improved for ice40, initial support for ecp5)	2019-09-29 11:26:22 -07:00
Eddie Hung	18ebb86edb	FDCE_1 does not have IS_CLR_INVERTED	2019-09-29 11:25:34 -07:00
Eddie Hung	f3e150d9a5	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-29 09:21:51 -07:00
Eddie Hung	79b6edb639	Big rework; flop info now mostly in cells_sim.v	2019-09-28 23:48:17 -07:00
Eddie Hung	c372e7baf9	Fix box name	2019-09-27 18:49:45 -07:00
Eddie Hung	8f5710c464	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-27 15:14:31 -07:00
Eddie Hung	b3d8a60cbd	Re-order	2019-09-27 14:32:07 -07:00
Eddie Hung	143f82def2	Missing an '&'	2019-09-26 11:13:08 -07:00
Eddie Hung	033aefc0f4	Typo	2019-09-26 10:34:14 -07:00
Eddie Hung	781dda6175	select once	2019-09-26 10:15:05 -07:00
Eddie Hung	27e5bf5aad	Stop trying to be too smart by prematurely optimising	2019-09-26 09:57:11 -07:00
Eddie Hung	53ea5daa42	Call 'wreduce' after mul2dsp to avoid unextend()	2019-09-25 14:04:36 -07:00
Eddie Hung	93363c94a2	Oops. Actually use __NAME__ in ABC_DSP48E1 macro	2019-09-25 10:33:16 -07:00
Eddie Hung	b41d2fb4e4	Add (* techmap_autopurge *) to abc_unmap.v too	2019-09-23 22:02:22 -07:00
Eddie Hung	11ac37733d	Add techmap_autopurge to outputs in abc_map.v too	2019-09-23 21:56:28 -07:00
Eddie Hung	27167848f4	Revert "Add a xilinx_finalise pass" ... This reverts commit 23d90e0439.	2019-09-23 19:52:55 -07:00
Eddie Hung	0f53893104	Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" ... This reverts commit 67c2db3486.	2019-09-23 19:52:55 -07:00
Eddie Hung	29db96fa1f	Revert "Vivado does not like zero width port connections" ... This reverts commit 895e2befa7.	2019-09-23 19:52:54 -07:00
Eddie Hung	895e2befa7	Vivado does not like zero width port connections	2019-09-23 19:04:07 -07:00
Eddie Hung	67c2db3486	Remove (* techmap_autopurge *) from abc_unmap.v since no effect	2019-09-23 18:56:18 -07:00
Eddie Hung	23d90e0439	Add a xilinx_finalise pass	2019-09-23 18:56:02 -07:00
Eddie Hung	4401e5f142	Grammar	2019-09-20 14:24:31 -07:00
Eddie Hung	289cf688b7	Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40	2019-09-20 09:02:29 -07:00
Eddie Hung	691686f92c	Tidy up, fix undriven	2019-09-19 20:04:52 -07:00
Eddie Hung	1602516a8b	$__ABC_REG to have WIDTH parameter	2019-09-19 19:37:45 -07:00
Eddie Hung	e09f80479e	Fix DSP48E1 timing by breaking P path if MREG or PREG	2019-09-19 18:59:28 -07:00
Eddie Hung	362a803779	Revert "Different approach to timing" ... This reverts commit 41256f48a5.	2019-09-19 18:33:38 -07:00
Eddie Hung	41256f48a5	Different approach to timing	2019-09-19 18:33:29 -07:00
Eddie Hung	5ca25b0c59	Suppress $anyseq warnings	2019-09-19 16:27:14 -07:00
Eddie Hung	595fb611a5	Use (* techmap_autopurge *) to suppress techmap warnings	2019-09-19 15:58:01 -07:00
Eddie Hung	c15a35db84	D is 25 bits not 24 bits wide	2019-09-19 15:55:49 -07:00