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D is 25 bits not 24 bits wide

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Eddie Hung 2019-09-19 15:55:49 -07:00
parent b88f0f6450
commit c15a35db84
1 changed files with 1 additions and 1 deletions
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2
techlibs/xilinx/dsp_map.v
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@ -32,7 +32,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
.A({{5{A[24]}}, A}),
.B(B),
.C(48'b0),
.D(24'b0),
.D(25'b0),
.P(P_48),
.INMODE(5'b00000),