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tests
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Add pattern detection support for DSP48E1 model, check against vendor
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2019-09-18 10:45:04 -07:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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abc9_map.v
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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abc9_model.v
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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abc9_unmap.v
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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abc9_xc7.box
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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abc9_xc7.lut
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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abc9_xc7_nowide.lut
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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arith_map.v
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Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21 16:19:45 -07:00 |
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brams_init.py
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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cells_map.v
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Use abc_{map,unmap,model}.v
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2019-08-20 12:39:11 -07:00 |
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cells_sim.v
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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cells_xtra.py
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
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2019-09-30 12:52:43 +02:00 |
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dsp_map.v
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D is 25 bits not 24 bits wide
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2019-09-19 15:55:49 -07:00 |
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lut_map.v
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Really permute Xilinx LUT mappings as default LUT6.I5:A6
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2019-06-18 11:48:48 -07:00 |
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lutrams.txt
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Work in progress for renaming labels/options in synth_xilinx
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2019-07-18 14:20:43 -07:00 |
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lutrams_map.v
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Work in progress for renaming labels/options in synth_xilinx
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2019-07-18 14:20:43 -07:00 |
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Makefile.inc
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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mux_map.v
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Change synth_xilinx's -nomux to -minmuxf <int>
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2019-06-24 10:04:01 -07:00 |
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synth_xilinx.cc
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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xc6s_brams.txt
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc6s_brams_bb.v
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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xc6s_brams_map.v
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RST -> RSTBRST for RAMB8BWER
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2019-07-29 16:05:44 -07:00 |
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xc6s_cells_xtra.v
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
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2019-09-30 12:52:43 +02:00 |
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xc6s_ff_map.v
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synth_xilinx: Support latches, remove used-up FF init values.
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2019-09-30 12:52:43 +02:00 |
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xc6v_cells_xtra.v
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
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2019-09-30 12:52:43 +02:00 |
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xc7_brams.txt
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc7_brams_bb.v
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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xc7_brams_map.v
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc7_cells_xtra.v
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
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2019-09-30 12:52:43 +02:00 |
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xc7_ff_map.v
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synth_xilinx: Support latches, remove used-up FF init values.
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2019-09-30 12:52:43 +02:00 |
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xcu_cells_xtra.v
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
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2019-09-30 12:52:43 +02:00 |
