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yosys/techlibs/xilinx
2019-10-04 17:21:14 -07:00
..
tests
.gitignore
abc9_map.v Fix merge issues 2019-10-04 17:21:14 -07:00
abc9_model.v
abc9_unmap.v Fix merge issues 2019-10-04 17:21:14 -07:00
abc9_xc7.box
abc9_xc7.lut
abc9_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v
cells_sim.v
cells_xtra.py
dsp_map.v
lut_map.v
lutrams.txt
lutrams_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc
xc6s_brams.txt
xc6s_brams_bb.v
xc6s_brams_map.v
xc6s_cells_xtra.v
xc6s_ff_map.v
xc6v_cells_xtra.v
xc7_brams.txt
xc7_brams_bb.v
xc7_brams_map.v
xc7_cells_xtra.v
xc7_ff_map.v
xcu_cells_xtra.v