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Code Activity
7629 commits 98 branches 53 tags 41 MiB
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710 commits

Author SHA1 Message Date
Eddie Hung cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427 
Refactor peepopt_dffmux and be sensitive to \init when trimming
 2019-10-08 12:38:29 -07:00
Eddie Hung 4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync 
async2sync to be called by equiv_opt only when -async2sync given
 2019-10-08 10:53:44 -07:00
Eddie Hung 5c68da4150 Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf 2019-10-05 09:27:12 -07:00
Eddie Hung 045f344038 Use sat -tempinduct and comments for why equiv_opt not sufficient 2019-10-03 11:11:50 -07:00
Eddie Hung bd5889640b Disable equiv check for ice40 latches 2019-10-03 10:45:53 -07:00
Eddie Hung 5d680590d6 Use equiv_opt -async2sync for xilinx 2019-10-03 10:30:33 -07:00
Clifford Wolf 0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select 
Add -select option to aigmap
 2019-10-03 11:54:04 +02:00
Eddie Hung e9645c7fa7 Fix broken CI, check reset even for constants, trim rstmux 2019-10-02 21:26:26 -07:00
Eddie Hung e4bd5aaebf Fix test 2019-10-02 18:12:25 -07:00
Eddie Hung c6a55d948a Merge branch 'eddie/fix_sat_init' into eddie/fix1427 2019-10-02 18:07:38 -07:00
Eddie Hung f6fabc8fda Update test 2019-10-02 18:03:45 -07:00
Eddie Hung e730a595ee Add test 2019-10-02 18:01:41 -07:00
Eddie Hung c28d4b8047 Add test that is expecting to fail 2019-10-02 14:52:40 -07:00
Eddie Hung a4f2f7d23c Extend test with renaming cells with prefix too 2019-10-02 12:43:18 -07:00
Eddie Hung 369652d4b9 Add test 2019-09-30 17:20:39 -07:00
Eddie Hung 8b239ee707 Add quick test 2019-09-30 15:34:04 -07:00
whitequark 5c5881695d
Merge pull request #1406 from whitequark/connect_rpc 
rpc: new frontend
 2019-09-30 17:38:20 +00:00
whitequark 99a7f39084 rpc: new frontend. 
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.

Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
 2019-09-30 15:53:11 +00:00
Eddie Hung 6216e45eda Add latch test modified from #1363 2019-09-30 12:52:43 +02:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Marcin Kościelnicki fd0e3a2c43 Fix _TECHMAP_REMOVEINIT_ handling. 
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.

Fixes the problem identified in #1396.
 2019-09-27 18:34:12 +02:00
Miodrag Milanovic 7f0eec8270 Change order of parameters, to work on other os 2019-09-27 11:31:55 +02:00
Eddie Hung a009314597
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40 
ICE40 tests. adffs test update (equiv_opt -multiclock).
 2019-09-25 16:43:24 -07:00
SergeyDegtyar b66364ada2 Change sync controls to async. 2019-09-25 14:43:26 +03:00
SergeyDegtyar fc6ebf8268 adffs test update (equiv_opt -multiclock). 2019-09-24 14:55:32 +03:00
Eddie Hung bcee87a457 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-23 10:58:28 -07:00
Eddie Hung 7c8de1dd18 Hell let's add the original #1381 testcase too 2019-09-20 17:58:51 -07:00
Eddie Hung 6258e6a7e2 Add testcase 2019-09-20 17:51:45 -07:00
Eddie Hung 4100825b81 Add more complicated macc testcase 2019-09-19 22:39:15 -07:00
Eddie Hung 2f98f9deee Add mac.sh and macc_tb.v for testing 2019-09-19 18:08:16 -07:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 65fa8adf6c Format macc.v 2019-09-19 11:02:14 -07:00
Marcin Kościelnicki c9f9518de4 Added extractinv pass 2019-09-19 04:02:48 +02:00
Eddie Hung c663a3680b Remove stat 2019-09-18 12:44:34 -07:00
Eddie Hung f7dbfef792 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:40:21 -07:00
Eddie Hung b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext 
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
 2019-09-18 12:40:08 -07:00
Eddie Hung c9fe4d7992 Add .gitignore 2019-09-18 12:11:33 -07:00
Eddie Hung c3cba7ab93 Refine macc testcase 2019-09-18 12:07:25 -07:00
Eddie Hung f492567c87 Oops 2019-09-13 18:19:07 -07:00
Eddie Hung a2eee9ebef Add counter-example from @cliffordwolf 2019-09-13 16:41:10 -07:00
Eddie Hung 14d72c39c3 Revert "Make one check $shift(x)? only; change testcase to be 8b" 
This reverts commit e2c2d784c8.
 2019-09-13 16:33:18 -07:00
Eddie Hung a1123b095c Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-12 12:11:11 -07:00
David Shah 6044fff074
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock 
Add equiv_opt -multiclock
 2019-09-12 12:26:28 +01:00
Eddie Hung 7d644f40ed Add AREG=2 BREG=2 test 2019-09-11 17:05:47 -07:00
Eddie Hung c0f26c2da8 Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-11 13:37:11 -07:00
Eddie Hung bdb5e0f29c Cope with presence of reset muxes too 2019-09-11 13:36:37 -07:00
Eddie Hung f46ef47893 Add more tests 2019-09-11 13:22:41 -07:00
Marcin Kościelnicki f72765090c Add -match-init option to dff2dffs. 2019-09-11 19:38:20 +02:00
Eddie Hung 6a95ecd41d Update test with a/b reset 2019-09-11 10:13:13 -07:00
Eddie Hung 36d6db7f8a Extend test for RSTP and RSTM 2019-09-11 09:09:08 -07:00