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Merge remote-tracking branch 'origin/master' into xc7dsp

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Eddie Hung 2019-09-12 12:11:11 -07:00
commit a1123b095c
9 changed files with 110 additions and 13 deletions
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2
tests/ice40/div_mod.ys
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@ -4,6 +4,6 @@ flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 62 t:SB_LUT4
select -assert-count 59 t:SB_LUT4
select -assert-count 41 t:SB_CARRY
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D

50
tests/techmap/dff2dffs.ys Normal file
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@ -0,0 +1,50 @@
read_verilog << EOT
module top(...);
input clk;
input d;
input sr;
output reg q0, q1, q2, q3, q4, q5;
initial q0 = 1'b0;
initial q1 = 1'b0;
initial q2 = 1'b1;
initial q3 = 1'b1;
initial q4 = 1'bx;
initial q5 = 1'bx;
always @(posedge clk) begin
q0 <= sr ? 1'b0 : d;
q1 <= sr ? 1'b1 : d;
q2 <= sr ? 1'b0 : d;
q3 <= sr ? 1'b1 : d;
q4 <= sr ? 1'b0 : d;
q5 <= sr ? 1'b1 : d;
end
endmodule
EOT
proc
simplemap
design -save ref
dff2dffs
clean
select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
select -assert-count 1 w:q1 %x t:$__DFFS_PP1_ %i
select -assert-count 1 w:q2 %x t:$__DFFS_PP0_ %i
select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
design -load ref
dff2dffs -match-init
clean
select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
select -assert-count 0 w:q1 %x t:$__DFFS_PP1_ %i
select -assert-count 0 w:q2 %x t:$__DFFS_PP0_ %i
select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i

12
tests/various/equiv_opt_multiclock.ys Normal file
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@ -0,0 +1,12 @@
read_verilog <<EOT
module top(input clk, pre, d, output reg q);
always @(posedge clk, posedge pre)
if (pre)
q <= 1'b1;
else
q <= d;
endmodule
EOT
prep
equiv_opt -assert -multiclock -map +/simcells.v synth