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Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock

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Add equiv_opt -multiclock
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David Shah 2019-09-12 12:26:28 +01:00 • committed by GitHub
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2 changed files with 23 additions and 1 deletions
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tests/various/equiv_opt_multiclock.ys Normal file
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read_verilog <<EOT
module top(input clk, pre, d, output reg q);
always @(posedge clk, posedge pre)
if (pre)
q <= 1'b1;
else
q <= d;
endmodule
EOT
prep
equiv_opt -assert -multiclock -map +/simcells.v synth