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Author	SHA1	Message	Date
Emil J. Tywoniak	62f19cb3a9	modtools: fix port_del db erase	2026-02-18 12:20:36 +01:00
Emil J	33a2de9635	Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check ... blifparse: add bounds check	2026-02-18 12:18:05 +01:00
Akash Levy	650c636d39	Fixups	2026-02-18 01:12:35 -08:00
nella	01e89a8f9e	Remove cell mentions.	2026-02-18 09:29:35 +01:00
nella	2b4f481850	Cleanup docs.	2026-02-18 09:24:41 +01:00
Akash Levy	33c2c88fa4	Bump Yosys to latest from upstream	2026-02-17 23:41:39 -08:00
Akash Levy	c04975b78c	Remove custom mux opt_exprs	2026-02-17 20:41:29 -08:00
AdvaySingh1	6cb9fadded	Removed downstream signals causing equiv_opt failures due to feedback loop	2026-02-17 16:22:59 -08:00
AdvaySingh1	90dbb91cae	Changed min cone size	2026-02-17 16:22:05 -08:00
AdvaySingh1	2ab89e1146	Passing equiv_opt pass and speed boosts	2026-02-17 16:13:51 -08:00
AdvaySingh1	c8b6869e65	Removed optimizations from infer_ce.cc for profiling	2026-02-17 15:20:57 -08:00
AdvaySingh1	a8e4fccc56	Removed simulation and isValidGatingSignal function	2026-02-17 14:07:22 -08:00
AdvaySingh1	fa9e7a77d7	Removed normal clockgate pass options form sate_clockgate pass	2026-02-17 13:43:22 -08:00
AdvaySingh1	efcabb270f	Added caching of simulation runs for speed	2026-02-17 13:38:32 -08:00
AdvaySingh1	dc4ca2c621	Added TODO for eliminating false paths	2026-02-17 12:42:20 -08:00
AdvaySingh1	499e83a549	Switched to using CE module. Mostly retaining SAT gates. Still needs speedup	2026-02-17 12:41:59 -08:00
AdvaySingh1	e755f6c42e	Added initial simulation. Incorrect simulation -- changed the number of accedpted results as well as increasing runtime	2026-02-17 12:14:53 -08:00
AdvaySingh1	2212d85626	Changed configurations to match the OpenROAD project	2026-02-17 11:57:56 -08:00
AdvaySingh1	144db54c4e	Changed to inverse hashing for more flexibility	2026-02-17 11:53:06 -08:00
AdvaySingh1	f0de3ae8de	Initial sat_clockgate pass pre speed optimization	2026-02-17 11:19:18 -08:00
AdvaySingh1	cc6605f8e2	Added passing on the args into the clockgate pass so there's an icg cell for the mapping	2026-02-17 10:49:18 -08:00
AdvaySingh1	2ab34262ec	Added profiling info before and after sat_clockgate pass	2026-02-17 09:23:32 -08:00
Emil J. Tywoniak	77f64de997	satgen: move report_missing_model here from equiv.h	2026-02-16 17:01:09 +01:00
Emil J. Tywoniak	81ea922512	sat: use the same cell import warnings as equiv	2026-02-16 16:54:26 +01:00
Miodrag Milanovic	63068f9b8f	count relative to version tag, and ignore non existing	2026-02-16 16:44:33 +01:00
nella	e6e57b33e3	document abc --keep-going pdr [sc-220].	2026-02-15 09:00:04 +01:00
AdvaySingh1	3567960671	Changed hashing from string to pair with vector and bool	2026-02-13 17:01:58 -08:00
AdvaySingh1	91d8241a9a	Revert "Added hashing for already seen paths. ODO: add profiling to see if this is effective" ... This reverts commit 56502440b3.	2026-02-13 16:34:38 -08:00
AdvaySingh1	5ce8aada27	Added profiling for literal count	2026-02-13 16:34:15 -08:00
AdvaySingh1	3442bc3a85	Changed indexing to be based on the literal ID in EZSat and sorted to allow better hashing	2026-02-13 16:15:31 -08:00
AdvaySingh1	80fbdf7e6a	Removed duplication of vectors and called clockgate pass post creating enable signals	2026-02-13 15:33:45 -08:00
AdvaySingh1	56502440b3	Added hashing for already seen paths. ODO: add profiling to see if this is effective	2026-02-13 15:32:54 -08:00
Akash Levy	5debd619e5	Add workaround for Liberty duplication	2026-02-13 06:51:42 -08:00
Miodrag Milanović	ac96f318ef	Merge pull request #5676 from YosysHQ/emil/unit-test-by-default ... Run unit tests on make test	2026-02-13 15:02:50 +01:00
Miodrag Milanovic	0090aa96b6	Remove version bump action	2026-02-13 14:22:33 +01:00
Miodrag Milanovic	adf8b6b0d8	Add +post to version if from tarbal	2026-02-13 14:22:10 +01:00
Miodrag Milanovic	c7d88ded94	Make version bump automatic	2026-02-13 14:21:41 +01:00
Akash Levy	0485576632	Revert rtlil changes	2026-02-13 04:14:14 -08:00
Akash Levy	2b247d165b	Merge from main	2026-02-13 04:14:08 -08:00
Akash Levy	b8d83c1d5b	Fix cell naming issues	2026-02-13 01:05:51 -08:00
Akash Levy	e81b5b810d	Lack of node retention should only be a warning	2026-02-13 01:04:59 -08:00
Chris Hathhorn	1e852cef16	Fix segfault from shift with 0-width signed arg. ... Fixes #5684.	2026-02-12 22:03:42 -06:00
AdvaySingh1	fca02c94df	Notes for TODOS	2026-02-12 17:04:50 -08:00
github-actions[bot]	e2f0c4d9a0	Bump version	2026-02-13 00:35:27 +00:00
AdvaySingh1	feffbbe32c	Added initial impl based on OpenROAD	2026-02-12 16:12:50 -08:00
AdvaySingh1	d7277fcb3a	Added explanation for safe-gating vs exact-gating	2026-02-12 15:20:39 -08:00
AdvaySingh1	0396bf48d1	Added notes.txt	2026-02-12 14:28:37 -08:00
AdvaySingh1	e4734e6ca9	Added comments explaining the MUX network repair Idea to see if there's a combinational circuit out of the input values which can serve as the enable signal	2026-02-12 12:49:15 -08:00
AdvaySingh1	514c01efd2	Added prune expressions list TODO	2026-02-12 12:14:25 -08:00
AdvaySingh1	745f17a34e	Changed input_set_is_enable_exact to XOR Mitter	2026-02-12 11:10:10 -08:00