tondapusili
f46b8d2a44
silimate: add opt_timing_balance pass and tests
2026-02-27 09:13:39 -08:00
Miodrag Milanović
687a36af38
Merge pull request #5711 from YosysHQ/gowin_warning
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gowin: remove spurious warning
2026-02-27 14:04:27 +01:00
Miodrag Milanovic
7f1f247c56
gowin: remove spurious warning
2026-02-27 13:12:32 +01:00
Miodrag Milanović
2dd71c3ba2
Merge pull request #5709 from YosysHQ/update_abc
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Update ABC as per 2026-02-27
2026-02-27 08:32:34 +01:00
Miodrag Milanovic
b3caec1a93
Update ABC as per 2026-02-27
2026-02-27 07:55:34 +01:00
Andrew Pullin
5970be33fb
abc9: preserve topological-loop asserts with targeted SCC fallback
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A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.
Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).
To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.
Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
2026-02-26 22:30:32 -08:00
Akash Levy
0c663bef4a
Merge pull request #110 from Silimate/negopt_log_flush
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Added log flushes after each negopt pass for clearer logging
2026-02-26 16:09:34 -08:00
Stan Lee
29a1c69f74
move log flush to better spot
2026-02-26 16:01:37 -08:00
Stan Lee
b11eef4fe1
fix bug
2026-02-26 16:00:27 -08:00
tondapusili
2f276d0723
Added log flushes after each negopt pass for clearer logging
2026-02-25 12:15:46 -08:00
nella
2c52546e2a
Fix docs.
2026-02-25 16:42:05 +01:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
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equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Miodrag Milanović
fd1ac58767
Merge pull request #5706 from YosysHQ/remove-flake-lock
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Remove already disabled CI job
2026-02-25 11:15:33 +01:00
Miodrag Milanovic
31f7d0d92d
Remove already disabled CI job
2026-02-25 10:36:46 +01:00
Gus Smith
366f98ae25
ADd clarification
2026-02-23 11:51:54 -08:00
Gus Smith
c0f1654028
Expand test into three tests for three cases
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(1) no check, (2) check with warning, (3) check
with error. Previously the single test was not
testing all cases, as it was exiting after the
first error.
2026-02-23 10:27:36 -08:00
Miodrag Milanović
53d8eb43ff
Merge pull request #5702 from YosysHQ/verific_build_all
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Check verific configurations
2026-02-23 09:41:59 +01:00
Miodrag Milanovic
b51110a50b
Build various Verific configurations
2026-02-23 09:01:55 +01:00
Krystine Sherwin
fd311c5501
tests/arch/gowin: Add wr_en test
2026-02-22 09:00:37 +01:00
Krystine Sherwin
2386923b8f
gowin: Fix bram ADA byte enables
2026-02-22 09:00:37 +01:00
Akash Levy
0b46d8b201
Merge pull request #109 from Silimate/clkgate_attr
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Added is_clock_gated attr to flops created via clockgate.cc pass
2026-02-20 17:02:02 -08:00
Akash Levy
c47dd20140
Merge pull request #108 from Silimate/icg_builtin_sim
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Added built in cell alongside sim support for cell
2026-02-20 17:01:20 -08:00
AdvaySingh1
ec537b189f
Added is_clock_gated attr to flops created via clockgate.cc pass
2026-02-20 11:34:50 -08:00
AdvaySingh1
8f5b8cb46c
Added is_clock_gated attr to flops created via clockgate.cc pass
2026-02-20 11:34:08 -08:00
Gus Smith
b454582f54
Detect undriven and error/warn
2026-02-20 11:00:59 -08:00
Gus Smith
cdc728b6f0
Suggest use of YW when possible
2026-02-20 09:33:51 -08:00
Miodrag Milanović
fb653c4181
Merge pull request #5700 from YosysHQ/wasi_speedup
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CI: WASI - Applying YoWASP changes to script
2026-02-20 18:00:24 +01:00
Miodrag Milanovic
68e47ebcfe
CI: WASI - Applying YoWASP changes to script
2026-02-20 15:23:45 +01:00
Miodrag Milanović
0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify
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abc9: verify post-mapping equivalence by default
2026-02-20 13:41:11 +01:00
Krystine Sherwin
094481739f
memory_libmap: Add -force-params
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Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
2026-02-20 10:57:00 +00:00
Emil J
13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks
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aigerparse: add some bounds checks
2026-02-20 11:53:49 +01:00
Emil J
74f7b0cf92
Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684
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Fix segfault from shift with 0-width signed arg.
2026-02-20 11:53:05 +01:00
Emil J
53509a9b2a
Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion
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modtools: fix database sanity
2026-02-20 10:49:28 +01:00
AdvaySingh1
84a03a6b9a
Merge branch 'icg_builtin_sim' into sat_clkgate
2026-02-19 11:51:49 -08:00
AdvaySingh1
b29514fafc
Added built in cell alongside sim support for cell
2026-02-19 11:48:35 -08:00
AdvaySingh1
d9867fc7c7
Merge branch 'main' into sat_clkgate
2026-02-19 09:43:22 -08:00
AdvaySingh1
5e58bf22e0
Changed param naming for consistancy
2026-02-19 09:42:59 -08:00
Akash Levy
723ddd74cf
Improve wreduce runtime
2026-02-19 01:03:26 -08:00
Miodrag Milanović
679156d323
Merge pull request #5686 from YosysHQ/version_bump
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Automatic version bump
2026-02-19 09:52:22 +01:00
Akash Levy
bf4ce9d6f7
Import uniquify fix
2026-02-19 00:24:32 -08:00
Akash Levy
3e9a5c68b1
Switch back to main Verific without VHDL support
2026-02-18 21:57:14 -08:00
Akash Levy
9a30512cff
Merge pull request #107 from Silimate/clkgate_node_retention
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Added node retention
2026-02-18 18:17:27 -08:00
AdvaySingh1
5769cdbea8
Added node retention
2026-02-18 16:05:56 -08:00
AdvaySingh1
d84e56ecac
Added naming for the new icg cells
2026-02-18 16:03:34 -08:00
Emil J. Tywoniak
abc7563a35
modtools: add ModIndex unit test
2026-02-18 22:15:44 +01:00
Emil J. Tywoniak
c75d80905a
modtools: fix database sanity on wire name swap
2026-02-18 21:23:21 +01:00
Akash Levy
b7098e8383
Merge branch 'YosysHQ:main' into main
2026-02-18 09:44:25 -08:00
AdvaySingh1
ee896b9eee
Removed sorting of similar candidate_gates for unnessessary optimization
2026-02-18 09:08:25 -08:00
Gus Smith
29a270c4b6
Merge pull request #5675 from rowanG077/add-missing-celledges
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kernel/celledges: cover more cell types
2026-02-18 07:50:41 -08:00
Miodrag Milanovic
5bb31485b7
Display repo and branch when applicable
2026-02-18 13:34:36 +01:00
