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Author SHA1 Message Date
Miodrag Milanović
ebfe5b2c06
Merge pull request #5774 from Silimate/atondapu/sim-cache-sigmap 
sim: cache sigmap in register_output_step_values
 2026-03-25 06:40:01 +00:00
AdvaySingh1
92e659f42a Added new port outputs anding the clock domain. TODO: fix if they belong to the same one and there's multiple 2026-03-24 20:00:24 -07:00
tondapusili
5b22e64d19 sim: cache sigmap in register_output_step_values 2026-03-24 16:10:11 -07:00
Robert O'Callahan
290fb0556d Prevent race on num_active_worker_threads_. 
The core issue here is that we need to ensure `num_active_worker_threads_`
is read before incrementing `done_workers`. See the comments
added in this PR to explain why, and why the resulting code is
race-free.
 2026-03-24 22:20:18 +00:00
AdvaySingh1
f7a9af5252 Make the signal_map flag optional 2026-03-24 14:39:21 -07:00
Miodrag Milanović
66306a8ca3
Merge pull request #5769 from Silimate/optimize_sim_pass 
sim: early return from checkSignals in sim mode
 2026-03-23 17:19:26 +00:00
Miodrag Milanović
cc915b4c76
Merge pull request #5717 from zaun/latch-support 
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
 2026-03-23 16:51:30 +00:00
Emil J
b44188110b
Merge pull request #5764 from YosysHQ/emil/constmap-error 
constmap: error if no -cell set
 2026-03-23 15:15:04 +00:00
Akash Levy
d99ba91fe7
Merge pull request #126 from Silimate/fix_mem_crash 
Safe parameter extraction in mem_from_cell
 2026-03-23 07:39:16 -04:00
Akash Levy
0ed1f1bfa4 Smallfixes 2026-03-23 03:51:49 -07:00
Akash Levy
91739e79cb Safe parameter extraction in mem_from_cell 2026-03-23 03:30:55 -07:00
Emil J
7b2ab9b245
Merge pull request #5763 from YosysHQ/emil/c-slow-init 
genrtlil: fast memory initialization
 2026-03-23 10:21:21 +00:00
AdvaySingh1
b9ba2c3552 Checked out abc to the yosys-experimental branch 2026-03-20 15:05:03 -07:00
AdvaySingh1
f9f31afcb4 Makefile pass changes 2026-03-20 12:42:51 -07:00
AdvaySingh1
2fc0591b2c Added clkmerge pass 2026-03-20 12:42:24 -07:00
tondapusili
69219e6be0 sim: early-return from checkSignals in sim mode 2026-03-20 12:32:49 -07:00
AdvaySingh1
e2a641f5a8 Added support for printing the cdc map file 2026-03-20 11:32:06 -07:00
AdvaySingh1
59dd03973e Added printing differnt clock domains in signal map 2026-03-20 10:37:47 -07:00
AdvaySingh1
daf5108434 Added inital cone_parition.cc pass. TODO: check with larger designs 2026-03-19 16:30:11 -07:00
AdvaySingh1
1711da5506 Moved the struct_partition pass to Silimate 2026-03-19 15:06:50 -07:00
AdvaySingh1
522ead01df Added small fixes 2026-03-19 15:04:13 -07:00
Akash Levy
fc320a7e8e
Merge pull request #123 from Silimate/accessor_helpers 
adding more fast Cell accessors and small refactoring to reduce code dup
 2026-03-19 17:40:18 -04:00
Emil J. Tywoniak
12b443e71c dfflibmap: consistent clk2fflogic usage in test 2026-03-19 19:48:25 +01:00
Emil J. Tywoniak
0e7f7c826d simcells: $dffsr and derivatives undefine S&R in logic tables 2026-03-19 19:27:30 +01:00
Miodrag Milanović
5fd39ff3e1
Merge pull request #5766 from YosysHQ/upgrade_ci 
Upgrade CI actions
 2026-03-19 18:06:50 +00:00
AdvaySingh1
8536ab69c1 Added -o option for output file in struct_partition 2026-03-19 10:09:11 -07:00
AdvaySingh1
26db947b57 Added zinit 2026-03-19 10:08:52 -07:00
Akash Levy
7771a489e8
Merge pull request #124 from Silimate/sim 
Add debugging code before assertion
 2026-03-19 12:45:49 -04:00
AdvaySingh1
52fad78b40 Removed is_port for non-trigger outputs. TODO: add a flag which does this so POs are only those ones 2026-03-19 09:23:12 -07:00
Emil J
dc77140275
Merge pull request #5731 from YosysHQ/nella/wall-clock 
Implement wall clock time measurement
 2026-03-19 16:21:26 +00:00
nella
ee0461eb00 Change time log format. 2026-03-19 14:38:22 +01:00
nella
d6ab610622 Implement wall clock time meas. 2026-03-19 14:38:22 +01:00
Miodrag Milanovic
2a8024ea4a Upgrade CI actions 2026-03-19 12:22:57 +01:00
Lofty
f560cba952
Merge pull request #5757 from YosysHQ/lofty/abc9-refactor-3 
abc9: remove -fast [sc-269]
 2026-03-19 08:41:45 +00:00
Lofty
27210627e5 abc9: remove -fast 2026-03-19 07:30:23 +00:00
Lofty
8d1d5a25e5
Merge pull request #5760 from YosysHQ/lofty/abc-refactor-2 
abc: remove -S [sc-269]
 2026-03-19 07:26:54 +00:00
Lofty
05de1c4ae2
Merge pull request #5759 from YosysHQ/lofty/abc9-refactor-4 
abc9: remove abc9.if.C [sc-269]
 2026-03-19 07:26:37 +00:00
AdvaySingh1
dc73249d8f Added support for printing the signal map 2026-03-18 16:23:41 -07:00
Emil J. Tywoniak
4f4672d17b muxpack: fix wide Y port handling 2026-03-19 00:12:49 +01:00
Emil J. Tywoniak
7aaa0621d3 constmap: error if no -cell set 2026-03-19 00:01:14 +01:00
Emil J
9746bd3897
Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection 
setundef: respect selection for cells, processes, and connections
 2026-03-18 22:53:06 +00:00
Emil J. Tywoniak
ad7a776d73 genrtlil: even faster removeSignalFromCaseTree 2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
27737c6e2e rtlil: add remove2 unit test 2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
ea11453cef rtlil: faster remove2 2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
23ce4b8560 genrtlil: faster removeSignalFromCaseTree 2026-03-18 23:33:35 +01:00
Stan Lee
8268a79af5 debug before assertion 2026-03-18 14:06:18 -07:00
Miodrag Milanović
a141bd941c
Merge pull request #5761 from YosysHQ/fix_ci 
Check results properly
 2026-03-18 20:08:04 +00:00
AdvaySingh1
a3ffc5da30 Added new passes/sat/struct_partition.cc pass to propagate the ports out 2026-03-18 11:53:47 -07:00
Miodrag Milanović
4a6bd6a2fe
Merge pull request #5762 from YosysHQ/revert-5758-lofty/abc-refactor-1 
Revert "abc: remove -fast [sc-269]"
 2026-03-18 17:57:53 +00:00
Lofty
f9d930ba5a
Revert "abc: remove -fast [sc-269]" 2026-03-18 17:55:17 +00:00