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Author	SHA1	Message	Date
Lofty	c4cc53a72e	synth: fix after abc -fast removal	2026-03-18 17:59:58 +01:00
Miodrag Milanovic	bccfdef05d	Check results properly	2026-03-18 17:48:28 +01:00
Lofty	e05ed6b850	Merge pull request #5758 from YosysHQ/lofty/abc-refactor-1 ... abc: remove -fast [sc-269]	2026-03-18 15:09:36 +00:00
Lofty	18a7c54ebd	Merge pull request #5756 from YosysHQ/lofty/abc9-refactor-2 ... abc9: cleanup commented code [sc-269]	2026-03-18 14:46:06 +00:00
Lofty	0b3f103745	abc: remove -S	2026-03-18 14:40:23 +00:00
Lofty	93c762c7c1	abc9: remove abc9.if.C	2026-03-18 14:27:27 +00:00
Lofty	926814f1e4	abc9: cleanup commented code	2026-03-18 14:16:31 +00:00
Lofty	0ea739b7d9	abc: remove -fast	2026-03-18 14:15:42 +00:00
Lofty	150860c1c3	Merge pull request #5755 from YosysHQ/lofty/abc9-refactor-1 ... abc9_exe: fix typo	2026-03-18 12:25:44 +00:00
Lofty	e78690fc47	abc9_exe: fix typo	2026-03-18 11:44:13 +00:00
Stan Lee	f9d099503a	Merge branch 'main' of github.com:silimate/yosys into sim	2026-03-17 11:44:18 -07:00
Stan Lee	a45eaad9a7	Merge branch 'sim' of github.com:silimate/yosys into sim	2026-03-17 11:44:11 -07:00
Akash Levy	00e67a30d0	Merge pull request #121 from Silimate/autoscope ... dump the number of scopes/signals in the search space	2026-03-16 13:33:40 -07:00
Stan Lee	e5d3bb954e	correction	2026-03-16 12:05:27 -07:00
tondapusili	29b182fd9b	adding more fast Cell accessors and small refactoring to reduce code dup	2026-03-16 10:47:54 -07:00
Emil J	c8f715fed8	Merge pull request #5664 from rocallahan/parallel-opt-clean ... Parallelize `opt_clean` pass	2026-03-16 09:52:34 +00:00
Miodrag Milanović	06264cdb2e	Merge pull request #5746 from IAmMarcelJung/fabulous/add_frame_config_mux_bels ... fabulous: add frame_config_mux BEls	2026-03-16 08:21:01 +00:00
Akash Levy	521b1db5ee	Merge pull request #122 from Silimate/optimize_cell_accessors ... rtlil: add fast Cell accessors and SigSpec::const_ratio()	2026-03-13 16:45:26 -07:00
AdvaySingh1	aff1836869	Abc printing to normal file	2026-03-13 16:40:23 -07:00
AdvaySingh1	11af3b5872	Added abc logs	2026-03-13 16:37:05 -07:00
AdvaySingh1	8006d148de	New abc	2026-03-13 16:08:10 -07:00
tondapusili	5d25ae4db6	rtlil: add fast Cell accessors and SigSpec::const_ratio()	2026-03-13 15:56:55 -07:00
KrystalDelusion	1111a401f7	Merge pull request #5750 from calewis/return_things ... Fix missing return in NDEBUG case	2026-03-13 22:07:28 +00:00
Drew Lewis	4251cd69ed	Fix missing return in NDEBUG case ... Signed-off-by: Drew Lewis <cannada@google.com>	2026-03-13 19:51:49 +00:00
Stan Lee	bcf71dea85	dump the number of scopes/signals in the search space	2026-03-13 11:15:46 -07:00
Marcel Jung	49ecb1ac11	fabulous: add frame_config_mux BEls	2026-03-12 16:05:21 +01:00
Lofty	4716f4410f	Merge pull request #5741 from YosysHQ/lofty/quicklogic-mul-bugfix ... synth_quicklogic: fix small multiplier inference	2026-03-11 11:47:46 +00:00
Lofty	53939bd3ba	synth_quicklogic: fix small multiplier inference	2026-03-11 11:14:09 +00:00
Catherine	18d94fe9a4	Merge pull request #5740 from kivikakk/push-utvloulmsuqy ... cxxrtl: Suppress another un/signed comparison warning!	2026-03-11 10:27:27 +00:00
Asherah Connor	5c74446e57	cxxrtl: Suppress another un/signed comparison warning!	2026-03-11 20:50:09 +11:00
Catherine	4d725ee84d	Merge pull request #5739 from kivikakk/push-nsqznnrrssrn ... cxxrtl: Suppress un/signed comparison warning; this is positive	2026-03-11 09:00:22 +00:00
Asherah Connor	c5c104f560	cxxrtl: Suppress un/signed comparison warning; this is positive	2026-03-11 18:35:48 +11:00
Emil J. Tywoniak	498cb79abe	async2sync: explain dffsr control signal variable polarity	2026-03-09 20:18:56 +01:00
Emil J. Tywoniak	43ef4d2901	fixup! async2sync: $dffsr has undef output on S&R	2026-03-09 20:12:24 +01:00
Miodrag Milanović	de99d67bbd	Merge pull request #5733 from YosysHQ/update_abc ... Update ABC as per 2026-03-09	2026-03-09 12:42:13 +00:00
Miodrag Milanovic	fea0d18c0a	Update ABC as per 2026-03-09	2026-03-09 13:04:45 +01:00
abhinavputhran	314d01b35f	changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change	2026-03-08 20:14:03 -04:00
abhinavputhran	47c2257f82	setundef: more tests! and wire selection in -init mode	2026-03-08 19:41:31 -04:00
abhinavputhran	c23ba3f917	I think CI runs within the tests directory based on error so I changed the file path	2026-03-08 18:15:35 -04:00
Akash Levy	168d64ab19	Merge pull request #120 from Silimate/is_mostly_const_param ... rtlil: parameterize SigSpec::is_mostly_const	2026-03-06 18:37:18 -08:00
Akash Levy	7e6f82ad4d	Merge pull request #119 from Silimate/autoscope ... Autoscope Improvement	2026-03-06 16:19:57 -08:00
tondapusili	e394197bc5	rtlil: parameterize SigSpec::is_mostly_const	2026-03-06 15:51:58 -08:00
abhinavputhran	5048dac854	setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer	2026-03-06 18:12:03 -05:00
Stan Lee	b7984f12f8	greptile	2026-03-06 12:19:17 -08:00
AdvaySingh1	db039c5987	Added Makefile with passed required for SAT	2026-03-06 11:41:33 -08:00
Stan Lee	1592125e71	fix err	2026-03-06 10:36:29 -08:00
Stan Lee	69145403df	more updates	2026-03-06 10:32:28 -08:00
Stan Lee	c9330dc36f	oop	2026-03-06 10:30:49 -08:00
Stan Lee	20c1f3212f	cleaner with warning	2026-03-06 10:23:31 -08:00
Stan Lee	c3a9a6d90e	fix	2026-03-06 09:59:51 -08:00