1663 commits

Author	SHA1	Message	Date
Clifford Wolf	210dda286f	Use techmap -share_map in btor scripts	2014-01-24 15:52:16 +01:00
Clifford Wolf	6804edd5d4	Moved btor scripts to backends/btor/	2014-01-24 15:48:07 +01:00
Ahmed Irfan	aa3cb20e1e	slice bug corrected	2014-01-20 18:35:52 +01:00
Ahmed Irfan	c347f2825f	assert feature	2014-01-20 10:45:02 +01:00
Ahmed Irfan	9a689f33a5	verilog default options pull ... shift operator width issues	2014-01-17 19:32:35 +01:00
Ahmed Irfan	c7a2e582aa	slice error corrected	2014-01-16 20:16:01 +01:00
Ahmed Irfan	3a1490888d	width issues ... dff cell for more than one registers	2014-01-15 17:36:33 +01:00
Ahmed Irfan	661b5a993e	BTOR backend	2014-01-14 12:03:53 +01:00
Ahmed Irfan	06482c046b	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	2014-01-03 10:54:54 +01:00
Ahmed Irfan	ffd768ce86	btor	2014-01-03 10:52:44 +01:00
Clifford Wolf	74d0de3b74	Updated manual/command-reference-manual.tex	2013-12-28 12:14:47 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	b5afd75b0a	Fixed gentb_constant handling in autotest backend	2013-12-04 09:09:42 +01:00
Clifford Wolf	ed441346ca	Added dump -m and -n options	2013-11-29 10:33:36 +01:00
Clifford Wolf	41205afc39	Added proper dumping of signed/unsigned parameters to verilog backend	2013-11-24 17:47:22 +01:00
Clifford Wolf	0ef22c7609	Added support for signed parameters in ilang	2013-11-24 17:37:27 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	1e6836933d	Added modelsim support to autotest	2013-11-24 15:10:43 +01:00
Clifford Wolf	28093d9dd2	Added "top" attribute to mark top module in hierarchy	2013-11-24 05:03:43 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	40d9542647	Implemented $_DFFSR_ expression generator in verilog backend	2013-11-21 21:52:30 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	2864cb3b59	Silenced a gcc warning in spice backend	2013-11-09 12:01:50 +01:00
Clifford Wolf	ba305a7ca6	Improved comments on topological sort in edif backend	2013-11-04 08:34:15 +01:00
Clifford Wolf	cd0fe7d786	Added simple topological sort to edif backend	2013-11-03 22:01:32 +01:00
Clifford Wolf	1dcb683fcb	Write yosys version to output files	2013-11-03 21:41:39 +01:00
Clifford Wolf	eab536a203	Merge branch 'master' of github.com:cliffordwolf/yosys	2013-11-03 21:13:21 +01:00
Clifford Wolf	4a60e5842d	Ignore explicit unconnected ports in intersynth backend	2013-11-03 09:00:51 +01:00
Clifford Wolf	0efe16f118	Added placeholder check to dfflibmap and cleaned up some other placeholder checks	2013-10-31 12:27:07 +01:00
Clifford Wolf	d9fa1e5a1d	Fixed hex string generation bug in edif backend	2013-10-27 08:21:05 +01:00
Clifford Wolf	628b994cf6	Added support for complex set-reset flip-flops in proc_dff	2013-10-24 16:54:05 +02:00
Clifford Wolf	e9dede01ca	Fixed handling of boolean attributes (backends)	2013-10-24 11:27:30 +02:00
Clifford Wolf	eae43e2db4	Fixed handling of boolean attributes (kernel)	2013-10-24 10:59:27 +02:00
Clifford Wolf	e0f693cbb0	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	2013-10-18 12:13:34 +02:00
Clifford Wolf	5998c101a4	Added $sr, $dffsr and $dlatch cell types	2013-10-18 11:56:16 +02:00
Clifford Wolf	30b0de006f	Added -buf, -true and -false options to blif backend	2013-10-17 21:37:18 +02:00
Clifford Wolf	5dce6379aa	Improvements in EDIF backend	2013-09-17 13:07:12 +02:00
Clifford Wolf	dc767d4e4c	Added additional options to BLIF backend	2013-09-15 13:33:33 +02:00
Clifford Wolf	0ec5542ab4	Added BLIF backend	2013-09-15 13:13:01 +02:00
Clifford Wolf	28069e8a10	A couple of small fixes in SPICE backend	2013-09-15 12:19:06 +02:00
Clifford Wolf	2c9bd23801	Added spice testbench to techlibs/cmos	2013-09-14 13:29:11 +02:00
Clifford Wolf	bbe5aa446b	Added spice backend	2013-09-14 11:23:45 +02:00
Clifford Wolf	70476e2431	Merge branch 'master' of github.com:cliffordwolf/yosys	2013-09-03 19:10:25 +02:00
Clifford Wolf	73914d1a41	Added -selected option to various backends	2013-09-03 19:10:11 +02:00
Clifford Wolf	09e200797a	Encode large (>32 bits) parameters as hex string in edif backend	2013-08-28 08:48:49 +02:00
Clifford Wolf	2feee7415d	Improved edif backend	2013-08-27 14:22:11 +02:00
Clifford Wolf	39ee561169	More explicit integer output in verilog backend	2013-08-22 20:31:04 +02:00
Clifford Wolf	4f4cb2307f	Added correct encoding of identifiers in EDIF backend	2013-08-22 14:30:33 +02:00