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Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_

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This commit is contained in:
Clifford Wolf 2013-10-18 12:13:34 +02:00
parent 5998c101a4
commit e0f693cbb0
3 changed files with 181 additions and 0 deletions
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backends/verilog/verilog_backend.cc
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@ -573,6 +573,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
return true;
}
// FIXME: $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
// FIXME: $sr, $dffsr, $dlatch, $memrd, $memwr, $mem, $fsm
return false;