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Renamed "placeholder" to "blackbox"

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This commit is contained in:
Clifford Wolf 2013-11-22 15:01:12 +01:00
parent c854ad2e7e
commit 295e352ba6
12 changed files with 27 additions and 27 deletions
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2
backends/blif/blif.cc
View file

@ -300,7 +300,7 @@ struct BlifBackend : public Backend {
for (auto module_it : design->modules)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (module->processes.size() != 0)

6
backends/edif/edif.cc
View file

@ -121,7 +121,7 @@ struct EdifBackend : public Backend {
for (auto module_it : design->modules)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (top_module_name.empty())
@ -135,7 +135,7 @@ struct EdifBackend : public Backend {
for (auto cell_it : module->cells)
{
RTLIL::Cell *cell = cell_it.second;
if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) {
if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
lib_cell_ports[cell->type];
for (auto p : cell->connections) {
if (p.second.width > 1)
@ -233,7 +233,7 @@ struct EdifBackend : public Backend {
fprintf(f, " (technology (numberDefinition))\n");
for (auto module : sorted_modules)
{
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
SigMap sigmap(module);

2
backends/intersynth/intersynth.cc
View file

@ -132,7 +132,7 @@ struct IntersynthBackend : public Backend {
RTLIL::Module *module = module_it.second;
SigMap sigmap(module);
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
continue;

4
backends/spice/spice.cc
View file

@ -57,7 +57,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
if (design->modules.count(cell->type) == 0)
{
log("Warning: no (placeholder) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
for (auto &conn : cell->connections) {
RTLIL::SigSpec sig = sigmap(conn.second);
@ -178,7 +178,7 @@ struct SpiceBackend : public Backend {
for (auto module_it : design->modules)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (module->processes.size() != 0)

14
backends/verilog/verilog_backend.cc
View file

@ -941,9 +941,9 @@ struct VerilogBackend : public Backend {
log(" without this option all internal cells are converted to verilog\n");
log(" expressions.\n");
log("\n");
log(" -placeholders\n");
log(" usually modules with the 'placeholder' attribute are ignored. with\n");
log(" this option set only the modules with the 'placeholder' attribute\n");
log(" -blackboxes\n");
log(" usually modules with the 'blackbox' attribute are ignored. with\n");
log(" this option set only the modules with the 'blackbox' attribute\n");
log(" are written to the output file.\n");
log("\n");
log(" -selected\n");
@ -960,7 +960,7 @@ struct VerilogBackend : public Backend {
attr2comment = false;
noexpr = false;
bool placeholders = false;
bool blackboxes = false;
bool selected = false;
reg_ct.clear();
@ -988,8 +988,8 @@ struct VerilogBackend : public Backend {
noexpr = true;
continue;
}
if (arg == "-placeholders") {
placeholders = true;
if (arg == "-blackboxes") {
blackboxes = true;
continue;
}
if (arg == "-selected") {
@ -1002,7 +1002,7 @@ struct VerilogBackend : public Backend {
fprintf(f, "/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if (it->second->get_bool_attribute("\\placeholder") != placeholders)
if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
continue;
if (selected && !design->selected_whole_module(it->first)) {
if (design->selected_module(it->first))