3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00

Added support for complex set-reset flip-flops in proc_dff

This commit is contained in:
Clifford Wolf 2013-10-24 16:54:05 +02:00
parent e679a5d046
commit 628b994cf6
3 changed files with 147 additions and 17 deletions

View file

@ -99,6 +99,10 @@ static void autotest(FILE *f, RTLIL::Design *design)
std::map<std::string, int> signal_out;
RTLIL::Module *mod = it->second;
if (mod->get_bool_attribute("\\gentb_skip"))
continue;
int count_ports = 0;
log("Generating test bench for module `%s'.\n", it->first.c_str());
for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) {
@ -290,7 +294,8 @@ static void autotest(FILE *f, RTLIL::Design *design)
fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n");
fprintf(f, "\t// $dumpvars(0, testbench);\n");
for (auto it = design->modules.begin(); it != design->modules.end(); it++)
fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
if (!it->second->get_bool_attribute("\\gentb_skip"))
fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
fprintf(f, "\t$finish;\n");
fprintf(f, "end\n\n");