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Added support for complex set-reset flip-flops in proc_dff
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parent
e679a5d046
commit
628b994cf6
3 changed files with 147 additions and 17 deletions
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@ -99,6 +99,10 @@ static void autotest(FILE *f, RTLIL::Design *design)
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std::map<std::string, int> signal_out;
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RTLIL::Module *mod = it->second;
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if (mod->get_bool_attribute("\\gentb_skip"))
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continue;
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int count_ports = 0;
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log("Generating test bench for module `%s'.\n", it->first.c_str());
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for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) {
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@ -290,7 +294,8 @@ static void autotest(FILE *f, RTLIL::Design *design)
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fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n");
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fprintf(f, "\t// $dumpvars(0, testbench);\n");
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for (auto it = design->modules.begin(); it != design->modules.end(); it++)
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fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
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if (!it->second->get_bool_attribute("\\gentb_skip"))
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fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
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fprintf(f, "\t$finish;\n");
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fprintf(f, "end\n\n");
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