Lofty
cd64a4db76
analogdevices: user retargeting
2026-01-27 00:25:08 +00:00
Lofty
c2db4daeb9
analogdevices: more housekeeping
2026-01-27 00:25:08 +00:00
Lofty
839a974702
analogdevices: remove some extra cells!
2026-01-27 00:25:08 +00:00
Lofty
4cdabf9376
test suite
2026-01-27 00:25:08 +00:00
Lofty
0047b645d4
synth_analogdevices: remove scopeinfo cells
2026-01-27 00:25:08 +00:00
Lofty
bf602c5a72
Create synth_analogdevices
2026-01-27 00:25:08 +00:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived
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Avoid `module_not_derived` on internal cells in techmap result
2026-01-26 14:48:40 -08:00
Emil J
5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main
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Add gatesi_mode to init gates under gates_mode in BLIF format
2026-01-26 23:30:11 +01:00
Emil J
29a9e42b64
Merge pull request #5628 from rocallahan/linux-perf-ctl
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Add `linux_perf` command to turn Linux perf recording on and off.
2026-01-26 19:32:55 +01:00
Emil J
673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates
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Don't update `used_signals` for retained wires in `rmunused_module_signals`.
2026-01-26 15:47:25 +01:00
Robert O'Callahan
32e96605d4
Don't update used_signals for retained wires in rmunused_module_signals.
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These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.
These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
Emil J
f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word
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lut2mux: add -word option
2026-01-23 17:24:41 +01:00
Robert O'Callahan
4f53612725
Add linux_perf command to turn Linux perf recording on and off.
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This is extremely useful for profiling specific passes.
2026-01-23 01:44:57 +00:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix
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abc: handle ABC script errors instead of hanging
2026-01-23 07:16:48 +13:00
KrystalDelusion
98f848e503
Merge pull request #5546 from YosysHQ/krys/nested_packages
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Document nesting packages as unsupported
2026-01-23 07:16:22 +13:00
github-actions[bot]
a6fc695522
Bump version
2026-01-22 00:28:34 +00:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon
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Add debugon pass for persistent debug logging
2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree
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Add opt_balance_tree pass
2026-01-21 17:34:08 +01:00
Miodrag Milanović
2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy
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Avoid spurious copy in `IdStringCollector::trace_named()`
2026-01-21 08:30:07 +01:00
Robert O'Callahan
2c0448a81b
Avoid spurious copy in IdStringCollector::trace_named()
2026-01-21 03:31:56 +00:00
github-actions[bot]
57ac113b7f
Bump version
2026-01-21 00:27:51 +00:00
Miodrag Milanović
bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017
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verific: add explicit System Verilog 2017 option
2026-01-20 14:44:46 +01:00
Miodrag Milanovic
d0fa4781c6
verific: Fix -sv2017 message and formatting
2026-01-20 08:07:26 +01:00
Gus Smith
491276983e
Add test
2026-01-19 18:34:55 -08:00
Martin Povišer
90673cb0a2
techmap: Use -icells mode of frontend instead of type fixup
2026-01-19 16:49:49 -08:00
Martin Povišer
f67d4bcfa4
verilog: Do not set module_not_derived on internal cells
2026-01-19 16:48:13 -08:00
github-actions[bot]
49e5950791
Bump version
2026-01-20 00:26:10 +00:00
Krystine Sherwin
0f478a5952
tests/bug5574: Fix for non threaded abc
2026-01-20 05:56:14 +13:00
Miodrag Milanovic
cc3038f468
verific: Fix -sv2017 message
2026-01-19 16:32:46 +01:00
Miodrag Milanović
2bde91b6ef
Merge pull request #5618 from YosysHQ/update_abc
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Update ABC as per 2026-01-19
2026-01-19 15:45:02 +01:00
nella
67d10a41e8
Merge pull request #5617 from YosysHQ/emil/consteval-description
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consteval: describe
2026-01-19 14:56:24 +01:00
Miodrag Milanovic
691983be14
Update ABC as per 2026-01-19
2026-01-19 12:08:24 +01:00
Emil J
7880f31acb
Merge pull request #5531 from YosysHQ/emil/shuffle-contributing-docs
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docs: shuffle and expand contributing info
2026-01-19 12:02:49 +01:00
Emil J. Tywoniak
c3f36afe7f
opt_balance_tree: mark experimental
2026-01-19 12:01:25 +01:00
Emil J. Tywoniak
befadf6d4d
consteval: describe
2026-01-19 12:00:18 +01:00
Miodrag Milanović
9355fa5037
Merge pull request #5616 from rocallahan/fix-unused-var-warning
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Fix warning about unused variable in `dffunmap`.
2026-01-19 08:24:48 +01:00
Robert O'Callahan
28c199fbbd
Fix warning about unused variable in dffunmap.
2026-01-19 03:25:09 +00:00
KrystalDelusion
8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err
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Improve error handling in sim
2026-01-19 09:51:12 +13:00
Miodrag Milanovic
d095d2c405
verific: add explicit System Verilog 2017 option
2026-01-16 07:56:53 +01:00
Natalia
ed64df737b
Add -on/-off modes to debug pass
2026-01-15 12:07:26 -08:00
Natalia
d5e1647d11
fix tests with truncation issues
2026-01-14 18:03:30 -08:00
github-actions[bot]
967b47d984
Bump version
2026-01-15 00:24:54 +00:00
Natalia
305b6c81d7
Refine width check to allow Y_WIDTH >= natural width
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Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).
This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
2026-01-14 14:58:53 -08:00
Natalia
60ac3670cb
Fix truncation issue in opt_balance_tree pass
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Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.
For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)
Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
2026-01-14 13:14:56 -08:00
Emil J. Tywoniak
ddf3c6c8b7
blif: add -gatesi test
2026-01-14 21:41:56 +01:00
kamay
e0077b188d
Add gatesi_mode in BLIF format
2026-01-14 21:41:56 +01:00
nella
763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string
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Add rtlil string getters
2026-01-14 19:00:47 +01:00
nella
210b733555
Add rtlil string getters
2026-01-14 15:37:18 +01:00
github-actions[bot]
4c1a18f01d
Bump version
2026-01-14 06:40:44 +00:00
Natalia Kokoromyti
6aef8ea8ab
Add missing <deque> include for MSVC compatibility
2026-01-13 15:31:46 -08:00
