clemens
8b1f77ebd2
cleanup. printf to errors or warnings
2025-08-16 09:40:03 +02:00
clemens
50fe9dd7f2
clean parsing code
2025-08-16 09:40:03 +02:00
clemens
5fc0e77c3d
add functionality to be able to use parameterised cells.
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cells can have their area as a function of the input port width.
2025-08-16 09:40:03 +02:00
clemens
a6e0ab5ea5
Update (sequential) area to be only local without -hierarchy
2025-08-16 09:09:57 +02:00
suisseWalter
f5b219f59e
Update passes/cmds/stat.cc
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Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
2025-08-16 08:36:06 +02:00
KrystalDelusion
7799c6e6ac
Merge pull request #5291 from YosysHQ/krys/rename_escape
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rename.cc: Fixup ports after -unescape
2025-08-16 12:19:49 +12:00
Emil J
70600bb596
Merge pull request #5239 from rocallahan/abc-incremental
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In the ABC pass, avoid scanning the entire module for each ABC run
2025-08-15 20:17:32 +02:00
Robert O'Callahan
dd88423334
Make OptMuxtree int-indexed vectors into hashtables
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For one of our large circuits, this reduced the time for an OPT_MUXTREE pass from
169s to 5s.
2025-08-14 23:09:15 +00:00
Krystine Sherwin
ec18d1aede
rename.cc: Fixup ports after -unescape
2025-08-15 10:48:32 +12:00
Robert O'Callahan
62c441107d
Build FfInitVals for the entire module once and use it for every ABC run.
2025-08-14 22:29:51 +00:00
Robert O'Callahan
2654bd5355
Compute is_port in AbcPass without iterating through all cells and wires in the module every time we run ABC.
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This does not scale when we run ABC thousands of times in a single AbcPass.
2025-08-14 22:29:45 +00:00
Robert O'Callahan
ac8259b02e
Preserve assign_map across ABC invocations.
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Currently `assign_map` is rebuilt from the module from scratch every time we invoke ABC.
That doesn't scale when we do thousands of ABC runs over large modules. Instead,
create it once and then maintain incrementally it as we update the module.
2025-08-14 22:27:04 +00:00
Robert O'Callahan
4de3ee093e
Mark kept FF output wires as ports directly instead of via the 'keep' attribute
2025-08-14 22:26:38 +00:00
clemens
71307b4a51
add Testcases
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Fix existing testcases
Fix edgecase where modules where counted as cells.
2025-08-13 14:46:01 +02:00
Emil J. Tywoniak
856fc43a87
rename: format vector slices consistently with HDL upto/downto direction
2025-08-13 11:11:53 +02:00
Jannis Harder
77089a8d03
rename: add -move-to-cell option in -wire mode
2025-08-13 11:11:52 +02:00
clemens
383d11c2ac
fix design overview in json.
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Fix some unknown cells apearing twice.
2025-08-13 10:09:02 +02:00
clemens
1eb8844e38
fix labeling in report
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fix design hierarchy containing wrong values.
remove left over debug print.
2025-08-13 08:36:26 +02:00
Robert O'Callahan
ccb23ffc1a
Fix indentation
2025-08-13 05:44:52 +00:00
Robert O'Callahan
885bb744e3
Make module a parameter of the function so we can change its constness in context
2025-08-13 05:44:52 +00:00
Robert O'Callahan
53c72c0d39
Move code in abc_module() that modifies the design into a new function extract()
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Splits up the big `abc_module()` function and isolates the code that modifies the design
after running ABC.
2025-08-13 05:44:52 +00:00
Robert O'Callahan
ceedcecfae
Move the input parameters to abc_module that are identical across modules to an AbcConfig struct.
2025-08-13 05:44:52 +00:00
Robert O'Callahan
4ba42c4752
Move ABC pass state to a struct instead of storing it in global variables.
2025-08-13 05:44:52 +00:00
Anhijkt
b3ca5ee0f1
opt_dff: fix timeout issue
2025-08-13 01:48:59 +03:00
Jannis Harder
1f876f3a22
abstract: Add -initstates option
2025-08-12 15:37:12 +02:00
Jannis Harder
256aa3e389
check: Limit detailed cell edge checking for $pmux and $bmux
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While these cells can't have a quadratic number of edges between A, B
and Y, they do have a quadratic number of edges between S and Y.
2025-08-12 14:38:20 +02:00
Emil J
fb024c4d55
Merge pull request #5135 from YosysHQ/emil/ast-ownership
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ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-08-12 10:58:12 +02:00
clemens
2a97987cf2
formatting and remove debug statements
2025-08-12 09:16:05 +02:00
clemens
a0dde68487
Improve STAT
2025-08-12 09:04:16 +02:00
Krystine Sherwin
20c2d2a6f3
test_cell: Add comment on $pmux
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`-simlib` also doesn't work.
2025-08-12 10:57:59 +12:00
Martin Povišer
c589714433
test_cell: Update to $macc_v2
2025-08-12 10:57:59 +12:00
Krystine Sherwin
db4ffaffd2
consteval: Fix $bwmux handling
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If the cell type has a S signal and hasn't already been handled, use `CellTypes::eval(cell, A, B, S)`.
2025-08-12 10:57:58 +12:00
Krystine Sherwin
014eadd8b9
test_cell: Fix $bweqx
2025-08-12 10:57:58 +12:00
Krystine Sherwin
22aa9fba3b
test_cell: Support more cell types
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Still unsupported:
- wide muxes (`$_MUX16_` and friends)
Partially supported types have comments in `test_cell.cc`.
Fix `CellTypes::eval() for `$_NMUX_`.
Fix `RTLIL::Cell::fixup_parameters()` for $concat, $bwmux and $bweqx.
2025-08-12 10:57:58 +12:00
Krystine Sherwin
481ecb51a7
test_cell: Disable $macc testing
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Needs updating to `$macc_v2`.
2025-08-12 10:57:58 +12:00
Emil J. Tywoniak
c8e0ac0c61
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-08-11 13:34:10 +02:00
KrystalDelusion
1ae82d7b9d
Merge pull request #5233 from YosysHQ/krys/equiv_assume
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Assumptions for equiv_*
2025-08-09 10:39:04 +12:00
Emil J
d68d28d05e
Merge pull request #5183 from YosysHQ/emil/test-diagnostics
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logger: add -expect types prefix-log, prefix-warning, prefix-error
2025-08-08 14:46:25 +02:00
Krystine Sherwin
e02f4469c0
equiv_simple: Avoid std::array
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VS build currently failing with `error C2641: cannot deduce template arguments for 'std::array'`.
Changing to `std::array<Cone, 2>` gives `error C2027: use of undefined type` instead.
2025-08-08 12:37:38 +12:00
Emil J. Tywoniak
fcd9f98245
equiv_simple: refactor
2025-08-08 01:35:33 +02:00
Emil J
1e58443397
Merge pull request #5264 from YosysHQ/krys/raise_error_always
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raise_error: Add -always
2025-08-07 11:43:04 +02:00
Krystine Sherwin
4ac100fe13
cutpoint: Track wire drivers
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Necessary to avoid multiple drivers being inserted when a blackbox has inout ports (like when importing an unknown module with `verific`).
If any bits of an inout port have a known driver, treat the port as an input.
If there are no bits with a known driver, treat the port as an output, and mark each bit as having a driver.
2025-08-06 18:11:05 +12:00
Krystine Sherwin
b1eeb7de3d
Less verbose equiv assumes
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both only print on the first step, and equiv_simple only prints if also verbose
2025-08-06 15:21:10 +12:00
Krystine Sherwin
93b39ad9b3
equiv_induct: Add -set-assumes option
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Uses mostly the same code as equiv_simple, but the assumes are already being imported so long as they're in the selection, so it's even easier.
2025-08-06 15:12:48 +12:00
Krystine Sherwin
3959d19291
Reapply "Add groups to command reference"
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This reverts commit 81f87ce6ed
2025-08-06 13:52:12 +12:00
Lofty
7537a49f0d
Merge pull request #5241 from Anhijkt/opt_dff-simplify-pt
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opt_dff: implement simplify_patterns
2025-08-04 09:44:57 +01:00
Krystine Sherwin
895dfd963f
raise_error: Add -always
2025-08-02 14:53:36 +12:00
Anhijkt
85e0e8ca67
typo
2025-07-30 21:40:20 +03:00
Anhijkt
bfff7a47f1
typo
2025-07-30 21:34:42 +03:00
Anhijkt
206d2a4553
opt_dff: refactor simplify_patterns
2025-07-30 21:31:34 +03:00
