mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Mark kept FF output wires as ports directly instead of via the 'keep' attribute

Browse source
This commit is contained in:
Robert O'Callahan 2025-07-26 09:34:37 +00:00
parent ccb23ffc1a
commit 4de3ee093e
1 changed files with 9 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

15
passes/techmap/abc.cc
View file

@ -291,12 +291,15 @@ void AbcModuleState::extract_cell(RTLIL::Module *module, RTLIL::Cell *cell, bool
return;
}
if (keepff)
for (auto &c : ff.sig_q.chunks())
if (c.wire != nullptr)
c.wire->attributes[ID::keep] = 1;
map_signal(ff.sig_q, type, map_signal(ff.sig_d));
int gate_id = map_signal(ff.sig_q, type, map_signal(ff.sig_d));
if (keepff) {
SigBit bit = ff.sig_q;
if (assign_map(bit).wire != nullptr) {
signal_list[gate_id].is_port = true;
}
if (bit.wire != nullptr)
bit.wire->attributes[ID::keep] = 1;
}
ff.remove();
return;