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Less verbose equiv assumes

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both only print on the first step, and equiv_simple only prints if also verbose
This commit is contained in:
Krystine Sherwin 2025-08-06 15:21:10 +12:00
parent f9e8127e2b
commit b1eeb7de3d
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2 changed files with 12 additions and 8 deletions
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10
passes/equiv/equiv_induct.cc
View file

@ -79,10 +79,12 @@ struct EquivInductWorker
}
if (set_assumes) {
RTLIL::SigSpec assumes_a, assumes_en;
satgen.getAssumes(assumes_a, assumes_en, step);
for (int i = 0; i < GetSize(assumes_a); i++)
log("Import constraint from assume cell: %s when %s.\n", log_signal(assumes_a[i]), log_signal(assumes_en[i]));
if (step == 1) {
RTLIL::SigSpec assumes_a, assumes_en;
satgen.getAssumes(assumes_a, assumes_en, step);
for (int i = 0; i < GetSize(assumes_a); i++)
log("Import constraint from assume cell: %s when %s.\n", log_signal(assumes_a[i]), log_signal(assumes_en[i]));
}
ez->assume(satgen.importAssumes(step));
}

10
passes/equiv/equiv_simple.cc
View file

@ -243,10 +243,12 @@ struct EquivSimpleWorker
}
if (set_assumes) {
RTLIL::SigSpec assumes_a, assumes_en;
satgen.getAssumes(assumes_a, assumes_en, step+1);
for (int i = 0; i < GetSize(assumes_a); i++)
log("Import constraint from assume cell: %s when %s.\n", log_signal(assumes_a[i]), log_signal(assumes_en[i]));
if (verbose && step == max_seq) {
RTLIL::SigSpec assumes_a, assumes_en;
satgen.getAssumes(assumes_a, assumes_en, step+1);
for (int i = 0; i < GetSize(assumes_a); i++)
log(" Import constraint from assume cell: %s when %s (%d).\n", log_signal(assumes_a[i]), log_signal(assumes_en[i]), step);
}
ez->assume(satgen.importAssumes(step+1));
}