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yosys/passes
Robert O'Callahan ac8259b02e Preserve assign_map across ABC invocations.
Currently `assign_map` is rebuilt from the module from scratch every time we invoke ABC.
That doesn't scale when we do thousands of ABC runs over large modules. Instead,
create it once and then maintain incrementally it as we update the module.
2025-08-14 22:27:04 +00:00
..
cmds ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
equiv equiv_simple: Avoid std::array 2025-08-08 12:37:38 +12:00
fsm io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
hierarchy Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
memory ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
opt Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
pmgen Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
proc Proc: Use selections consistently 2025-05-31 12:04:42 +12:00
sat Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
techmap Preserve assign_map across ABC invocations. 2025-08-14 22:27:04 +00:00
tests test_cell: Add comment on $pmux 2025-08-12 10:57:59 +12:00