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Code Activity
15284 commits 121 branches 59 tags 69 MiB
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1708 commits

Author SHA1 Message Date
Clifford Wolf
8d88fcb270 Added SatGen support for $anyconst 2016-07-27 15:52:20 +02:00
Clifford Wolf
9540be1d45 Removed $predict support from SatGen 2016-07-27 15:44:11 +02:00
Clifford Wolf
4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf
a7b0769623 Added "read_verilog -dump_rtlil" 2016-07-27 15:40:17 +02:00
Clifford Wolf
8537c4d206 Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() 2016-07-25 16:39:25 +02:00
Clifford Wolf
b1c432af56 Improvements in CellEdgesDatabase 2016-07-24 17:21:53 +02:00
Clifford Wolf
f162b858f2 Added CellEdgesDatabase API 2016-07-24 13:59:57 +02:00
Clifford Wolf
89deb412c6 Added satgen initstate support 2016-07-22 10:28:45 +02:00
Clifford Wolf
5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Ruben Undheim
a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
 2016-06-18 14:23:38 +02:00
Ruben Undheim
178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf
ebece2b8d5 Added $sop SAT model 2016-06-17 17:47:30 +02:00
Clifford Wolf
95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf
864eeadcd9 Added missing "#define HASHLIB_H" 2016-05-14 11:43:20 +02:00
Clifford Wolf
570014800a Include <cmath> in yosys.h 2016-05-08 10:50:39 +02:00
Clifford Wolf
f103bfb9ba Fixes for MXE build 2016-05-07 10:53:18 +02:00
Clifford Wolf
9aa4b3309c Added "yosys -D ALL" 2016-04-24 17:12:34 +02:00
Clifford Wolf
0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf
a07f893a5f Minor hashlib bugfix 2016-04-16 23:20:11 +02:00
Clifford Wolf
ace462237f Hashlib indenting fix 2016-04-05 13:25:23 +02:00
Clifford Wolf
2553319081 Added ScriptPass helper class for script-like passes 2016-03-31 11:16:34 +02:00
Clifford Wolf
6f1b6dc322 Added log_dump() support for dict<> and pool<> containers 2016-03-31 09:57:44 +02:00
Clifford Wolf
0db53284fd We have 2016 for a while now 2016-03-30 13:52:26 +02:00
Clifford Wolf
48dbc75bed Added .vhd file extension support 2016-03-30 13:24:49 +02:00
Clifford Wolf
95784437ac Merge pull request #137 from ravenexp/master 
Embed DATDIR make variable value into yosys binary.
 2016-03-28 16:54:23 +02:00
Sebastian Kuzminsky
73870c1edf fix a cut-n-paste error in the -h help 2016-03-26 11:15:35 -06:00
Sergey Kvachonok
963c0d2525 Embed DATDIR make variable value into yosys binary. 
Use it as the last resort in the share/ directory location search.
 2016-03-26 11:16:53 +03:00
Clifford Wolf
45af4a4acf Use easyer-to-read unoptimized ceil_log2() 
see here for details on the optimized version:
http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c
 2016-02-15 23:06:18 +01:00
Clifford Wolf
0c4b311242 Fixed more visual studio warnings 2016-02-14 09:35:25 +01:00
Clifford Wolf
bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf
0d7fd2585e Added "int ceil_log2(int)" function 2016-02-13 16:52:16 +01:00
Clifford Wolf
ba407da187 Added addBufGate module method 2016-02-02 11:26:07 +01:00
Clifford Wolf
01bcc5663f SigMap performance improvement 2016-02-01 10:10:20 +01:00
Clifford Wolf
ea492abcf0 hashlib mfp<> performance improvements 2016-02-01 10:03:03 +01:00
Clifford Wolf
13e15a24a2 Added reserve() method to haslib classes and 
calculate hashtable size based on entries capacity, not size
 2016-01-31 22:50:34 +01:00
Rick Altherr
3c48de8e21 rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) 
Converting to a pool<SigBit> is fairly expensive due to inserts somewhat
frequently causing rehashing.  Instead, walk through the pattern SigSpec
directly on a chunk-by-chunk basis and apply it to this SigSpec's
individual bits.  Using chunks for the pattern minimizes the number of
iterations in the outer loop.
 2016-01-31 09:20:16 -08:00
Rick Altherr
0265d7b100 rtlil: speed up SigSpec::sort_and_unify() 
std::set<> internally is often a red-black tree which is fairly
expensive to create but fast to lookup.  In the case of
sort_and_unify(), a set<> is constructed as a temporary object to
attempt to speed up lookups.  Being a temporarily, however, the cost of
creation far outweights the lookup improvement and is a net performance
loss.  Instead, sort the vector<> that already exists and then apply
std::unique().
 2016-01-31 09:20:16 -08:00
Rick Altherr
89dc40f162 rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*) 2016-01-31 09:20:16 -08:00
Rick Altherr
cd3e1095b0 rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*) 2016-01-31 09:20:16 -08:00
Clifford Wolf
5462399c88 Meaningless coding style change 2016-01-31 16:12:35 +01:00
Rick Altherr
43756559d8 rtlil: rewrite remove2() to avoid copying 2016-01-30 00:28:07 -08:00
Rick Altherr
12ebdef17c rtlil: duplicate remove2() for std::set<> 2016-01-29 23:06:40 -08:00
Rick Altherr
9e26147ccd rtlil: change IdString comparison operators to take references instead of copies 2016-01-29 23:06:40 -08:00
Clifford Wolf
33a5b28e25 Added default values for hashlib at() methods 2015-12-02 20:41:57 +01:00
Clifford Wolf
276101f032 Re-added SigMap::allbits() 2015-11-30 19:43:52 +01:00
Clifford Wolf
6459e3ac39 Removed dangling ';' in rtlil.h 2015-11-26 18:11:34 +01:00
Clifford Wolf
1e32e4bdae Improved SigMap performance 2015-10-28 11:21:55 +01:00