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17877 commits 138 branches 69 tags 63 MiB
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Author SHA1 Message Date
nella
a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
nataliakokoromyti
f3c87610f5 verific: allow mixed SV/VHDL in -f files 2026-01-24 23:46:45 -08:00
Robert O'Callahan
32e96605d4 Don't update used_signals for retained wires in rmunused_module_signals. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Emil J
f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
nella
0e4282d442 Add more opt_dff documentation. 2026-01-23 09:17:14 +01:00
Robert O'Callahan
4f53612725 Add linux_perf command to turn Linux perf recording on and off. 
This is extremely useful for profiling specific passes.
 2026-01-23 01:44:57 +00:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
KrystalDelusion
98f848e503
Merge pull request #5546 from YosysHQ/krys/nested_packages 
Document nesting packages as unsupported
 2026-01-23 07:16:22 +13:00
Akash Levy
5a6dffeecd Silimate mods to upstream opt_balance_tree pass 2026-01-21 23:34:34 -08:00
Akash Levy
4242d7022c
Merge branch 'YosysHQ:main' into main 2026-01-21 17:23:46 -08:00
Akash Levy
59fdd9105e
Merge pull request #95 from stanminlee/main 
Register annotation
 2026-01-21 17:23:35 -08:00
github-actions[bot]
a6fc695522 Bump version 2026-01-22 00:28:34 +00:00
Stan Lee
adab53eb96
Merge branch 'Silimate:main' into main 2026-01-21 16:12:32 -08:00
Akash Levy
c49055cb4e
Remove persist-credentials from checkout steps 
Removed 'persist-credentials: false' from multiple checkout steps.
 2026-01-21 16:11:54 -08:00
Stan Lee
a52689a1fa
Merge branch 'main' into main 2026-01-21 15:46:06 -08:00
Stan Lee
99cf75531f merge 2026-01-21 15:43:25 -08:00
Stan Lee
f026cebaf6 address comments 2026-01-21 15:16:45 -08:00
Akash Levy
947139aca1 Remove opt_balance_tree from silimate (now in opt) 2026-01-21 15:15:21 -08:00
Akash Levy
b11037e6c6 Merge remote-tracking branch 'upstream/main' 2026-01-21 15:13:57 -08:00
Stan Lee
f14eb4a7bb only check reg cells 2026-01-21 15:13:55 -08:00
Stan Lee
269b70c0f9 compiles 2026-01-21 12:32:38 -08:00
Stan Lee
0018037c16 minor changes 2026-01-21 12:25:28 -08:00
Stan Lee
e824c8e0d6 ready for review 2026-01-21 09:00:46 -08:00
Stan Lee
31e32af4a8 greptile 2026-01-21 08:54:43 -08:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
nella
f6eba53d1f Fix copyright header. 2026-01-21 14:52:19 +01:00
nella
2c12545cf3 opt_dff restructure. 2026-01-21 10:08:44 +01:00
Miodrag Milanović
2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy 
Avoid spurious copy in `IdStringCollector::trace_named()`
 2026-01-21 08:30:07 +01:00
Stan Lee
d2e8f9b8a8 first round fixes 2026-01-20 21:45:13 -08:00
Robert O'Callahan
2c0448a81b Avoid spurious copy in IdStringCollector::trace_named() 2026-01-21 03:31:56 +00:00
github-actions[bot]
57ac113b7f Bump version 2026-01-21 00:27:51 +00:00
Stan Lee
29061d3051 leave no room for err 2026-01-20 15:55:05 -08:00
Stan Lee
45bd3f4515 change splitcells pass to remove some bracket from register names in blast mode 2026-01-20 15:50:43 -08:00
Stan Lee
60a81a2676 reg rename pass reads from vcd for original widths 2026-01-20 15:35:13 -08:00
Stan Lee
a5106da733 line reduction 2026-01-20 11:56:57 -08:00
Stan Lee
0ea4bb8a2d comment 2026-01-20 11:55:54 -08:00
Stan Lee
80364c608e significantly cleaner 2026-01-20 11:29:56 -08:00
Miodrag Milanović
bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017 
verific: add explicit System Verilog 2017 option
 2026-01-20 14:44:46 +01:00
Miodrag Milanovic
d0fa4781c6 verific: Fix -sv2017 message and formatting 2026-01-20 08:07:26 +01:00
Gus Smith
491276983e Add test 2026-01-19 18:34:55 -08:00
Martin Povišer
90673cb0a2 techmap: Use -icells mode of frontend instead of type fixup 2026-01-19 16:49:49 -08:00
Martin Povišer
f67d4bcfa4 verilog: Do not set module_not_derived on internal cells 2026-01-19 16:48:13 -08:00
github-actions[bot]
49e5950791 Bump version 2026-01-20 00:26:10 +00:00
Stan Lee
c471014878 slightly cleaner 2026-01-19 12:58:36 -08:00
Stan Lee
6303eed1b4 works hierarchy 2026-01-19 12:22:22 -08:00
Stan Lee
186fc15f8f passes simple test 2026-01-19 12:10:48 -08:00
Stan Lee
e678e2a0c3 every step except wire connecting 2026-01-19 11:20:11 -08:00
Stan Lee
15026033a3 annotate original register width 2026-01-19 11:19:41 -08:00
Krystine Sherwin
0f478a5952
tests/bug5574: Fix for non threaded abc 2026-01-20 05:56:14 +13:00