364 commits

Author	SHA1	Message	Date
Eddie Hung	95644b00cb	OPMODE is port not param	2019-09-20 12:37:29 -07:00
Eddie Hung	eb597431f0	Do not run xilinx_dsp_cascadeAB for now	2019-09-20 12:18:37 -07:00
Eddie Hung	0bca366bcd	WIP for xiinx_dsp_cascadeAB	2019-09-20 12:07:14 -07:00
Eddie Hung	b0ad2592be	Run until convergence	2019-09-20 12:04:16 -07:00
Eddie Hung	1b892ca1be	Cleanup ice40_dsp.pmg	2019-09-20 12:03:45 -07:00
Eddie Hung	d88903e610	Cleanup xilinx_dsp	2019-09-20 12:03:25 -07:00
Eddie Hung	1809f463fb	More exceptions	2019-09-20 12:03:10 -07:00
Eddie Hung	70c5444b25	Update doc	2019-09-20 10:07:54 -07:00
Eddie Hung	ed187ef1cf	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	2019-09-20 10:00:09 -07:00
Eddie Hung	1844498c5f	Add an overload for port/param with default value	2019-09-20 09:59:42 -07:00
Eddie Hung	a0d3ecf8c6	Small cleanup	2019-09-20 08:41:28 -07:00
Eddie Hung	8cfcaf108e	Disable support for SB_MAC16 reset since it is async	2019-09-19 22:48:57 -07:00
Eddie Hung	a59f80834f	SB_MAC16 ffCD to not pack same as ffO	2019-09-19 22:39:47 -07:00
Eddie Hung	1b88211ec6	Clarify	2019-09-19 21:58:34 -07:00
Eddie Hung	34f9a8ceb2	Update doc for ice40_dsp	2019-09-19 21:57:11 -07:00
Eddie Hung	8a94ce7aa5	Add an index	2019-09-19 20:04:44 -07:00
Eddie Hung	c83a667555	Fix width of D	2019-09-19 18:08:46 -07:00
Eddie Hung	a8bc460805	Use ID() macro	2019-09-19 16:13:22 -07:00
Eddie Hung	37b0fc17e3	Re-enable sign extension for C input	2019-09-19 15:40:17 -07:00
Eddie Hung	64a72ed51e	Do not perform width-checks for DSP48E1 which is much more complicated	2019-09-19 14:50:11 -07:00
Eddie Hung	517ca49963	Remove TODO as check should not be necessary	2019-09-19 14:49:47 -07:00
Eddie Hung	307b2dc8e5	Revert index to select	2019-09-19 14:46:53 -07:00
Eddie Hung	ea5e5a212e	Cleanup xilinx_dsp too	2019-09-19 14:34:06 -07:00
Eddie Hung	1a0f7ed09c	Refactor ce{mux,pol} -> hold{mux,pol}	2019-09-19 14:27:25 -07:00
Eddie Hung	429c9852ce	Add HOLD/RST support for SB_MAC16	2019-09-19 14:02:55 -07:00
Eddie Hung	2766465a2b	Add support for SB_MAC16 CD and H registers	2019-09-19 12:14:33 -07:00
Eddie Hung	c8310a6e76	Refactor ice40_dsp.pmg	2019-09-19 12:00:48 -07:00
Eddie Hung	29d446d758	Cleanup	2019-09-19 10:39:00 -07:00
Eddie Hung	f7dbfef792	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-09-18 12:40:21 -07:00
Eddie Hung	b66c99ece0	Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext ... peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells	2019-09-18 12:40:08 -07:00
Eddie Hung	44bf4ac35c	Add doc on pattern detector for overflow	2019-09-18 12:35:24 -07:00
Eddie Hung	347cbf59bd	Check overflow condition is power of 2 without using int32	2019-09-18 12:16:03 -07:00
Eddie Hung	1f18736d20	Add support for overflow using pattern detector	2019-09-18 09:39:59 -07:00
Eddie Hung	0932e23dff	Separate dffrstmux from dffcemux, fix typos	2019-09-18 09:34:42 -07:00
Eddie Hung	14d72c39c3	Revert "Make one check $shift(x)? only; change testcase to be 8b" ... This reverts commit e2c2d784c8.	2019-09-13 16:33:18 -07:00
Eddie Hung	3a39073302	Set more ports explicitly	2019-09-12 17:10:43 -07:00
Eddie Hung	f3081c20e7	Add support for A1 and B1 registers	2019-09-11 17:16:46 -07:00
Eddie Hung	4369fc17d0	Raise a RuntimeError instead of AssertionError	2019-09-11 17:06:37 -07:00
Eddie Hung	6fa6bf483c	Rename {A,B} -> {A2,B2}	2019-09-11 16:21:24 -07:00
Eddie Hung	3a49aa6b4a	Tidy up	2019-09-11 14:20:49 -07:00
Eddie Hung	817ac7c5e0	Fix UB	2019-09-11 14:18:02 -07:00
Eddie Hung	63431fe42a	Fix UB	2019-09-11 14:17:45 -07:00
Eddie Hung	690b1a064d	Add PCOUT -> PCIN non-shifted cascading	2019-09-11 13:48:45 -07:00
Eddie Hung	c0f26c2da8	Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp	2019-09-11 13:37:11 -07:00
Eddie Hung	bdb5e0f29c	Cope with presence of reset muxes too	2019-09-11 13:36:37 -07:00
Eddie Hung	4937917cd8	Cleanup	2019-09-11 13:22:52 -07:00
Eddie Hung	e9eb855d38	Make unextend a udata	2019-09-11 13:06:49 -07:00
Eddie Hung	bbef0d2ac8	Only display log message if did_something	2019-09-11 12:29:26 -07:00
Eddie Hung	d232e6a6cd	Input registers to add DSP as new siguser to block upstream packing	2019-09-11 11:46:21 -07:00
Eddie Hung	e5bdb521fa	More cleanup	2019-09-11 10:55:45 -07:00