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https://github.com/YosysHQ/yosys
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Add support for A1 and B1 registers
This commit is contained in:
Eddie Hung
parent
4369fc17d0
commit
f3081c20e7
2 changed files with 105 additions and 24 deletions
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@ -259,7 +259,9 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("preAdd: %s\n", log_id(st.preAdd, "--"));
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log("ffAD: %s %s %s\n", log_id(st.ffAD, "--"), log_id(st.ffADcemux, "--"), log_id(st.ffADrstmux, "--"));
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log("ffA2: %s %s %s\n", log_id(st.ffA2, "--"), log_id(st.ffA2cemux, "--"), log_id(st.ffA2rstmux, "--"));
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log("ffA1: %s %s %s\n", log_id(st.ffA1, "--"), log_id(st.ffA1cemux, "--"), log_id(st.ffA1rstmux, "--"));
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log("ffB2: %s %s %s\n", log_id(st.ffB2, "--"), log_id(st.ffB2cemux, "--"), log_id(st.ffB2rstmux, "--"));
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log("ffB1: %s %s %s\n", log_id(st.ffB1, "--"), log_id(st.ffB1cemux, "--"), log_id(st.ffB1rstmux, "--"));
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log("ffC: %s %s %s\n", log_id(st.ffC, "--"), log_id(st.ffCcemux, "--"), log_id(st.ffCrstmux, "--"));
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log("ffD: %s %s %s\n", log_id(st.ffD, "--"), log_id(st.ffDcemux, "--"), log_id(st.ffDrstmux, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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@ -338,12 +340,14 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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if (rstmux) {
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SigSpec Y = rstmux->getPort("\\Y");
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SigSpec AB = rstmux->getPort(rstpol ? "\\A" : "\\B");
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SigSpec S = rstmux->getPort("\\S");
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if (!A.empty())
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A.replace(Y, AB);
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cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
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if (rstport != IdString()) {
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SigSpec S = rstmux->getPort("\\S");
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cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
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}
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}
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else
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else if (rstport != IdString())
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cell->setPort(rstport, State::S0);
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if (cemux) {
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SigSpec Y = cemux->getPort("\\Y");
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@ -368,16 +372,26 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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};
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if (st.ffA2) {
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SigSpec &A2 = cell->connections_.at("\\A");
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f(A2, st.ffA2, st.ffA2cemux, st.ffA2cepol, "\\CEA2", st.ffA2rstmux, st.ffArstpol, "\\RSTA");
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pm.add_siguser(A2, cell);
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cell->setParam("\\AREG", 1);
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SigSpec &A = cell->connections_.at("\\A");
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f(A, st.ffA2, st.ffA2cemux, st.ffA2cepol, "\\CEA2", st.ffA2rstmux, st.ffArstpol, "\\RSTA");
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pm.add_siguser(A, cell);
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if (st.ffA1) {
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f(A, st.ffA1, st.ffA1cemux, st.ffA1cepol, "\\CEA1", st.ffA1rstmux, st.ffArstpol, IdString());
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cell->setParam("\\AREG", 2);
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}
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else
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cell->setParam("\\AREG", 1);
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}
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if (st.ffB2) {
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SigSpec &B2 = cell->connections_.at("\\B");
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f(B2, st.ffB2, st.ffB2cemux, st.ffB2cepol, "\\CEB2", st.ffB2rstmux, st.ffBrstpol, "\\RSTB");
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pm.add_siguser(B2, cell);
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cell->setParam("\\BREG", 1);
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SigSpec &B = cell->connections_.at("\\B");
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f(B, st.ffB2, st.ffB2cemux, st.ffB2cepol, "\\CEB2", st.ffB2rstmux, st.ffBrstpol, "\\RSTB");
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pm.add_siguser(B, cell);
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if (st.ffB1) {
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f(B, st.ffB1, st.ffB1cemux, st.ffB1cepol, "\\CEB1", st.ffB1rstmux, st.ffBrstpol, IdString());
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cell->setParam("\\BREG", 2);
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}
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else
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cell->setParam("\\BREG", 1);
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}
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if (st.ffC) {
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SigSpec &C = cell->connections_.at("\\C");
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@ -406,14 +420,20 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log(" clock: %s (%s)", log_signal(st.clock), "posedge");
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if (st.ffA2)
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if (st.ffA2) {
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log(" ffA2:%s", log_id(st.ffA2));
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if (st.ffA1)
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log(" ffA1:%s", log_id(st.ffA1));
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}
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if (st.ffAD)
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log(" ffAD:%s", log_id(st.ffAD));
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if (st.ffB2)
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if (st.ffB2) {
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log(" ffB2:%s", log_id(st.ffB2));
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if (st.ffB1)
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log(" ffB1:%s", log_id(st.ffB1));
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}
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if (st.ffC)
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log(" ffC:%s", log_id(st.ffC));
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@ -449,17 +469,18 @@ struct XilinxDspPass : public Pass {
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log("\n");
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log(" xilinx_dsp [options] [selection]\n");
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log("\n");
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log("Pack input registers (A, B, C, D, AD; with optional enable/reset), pipeline\n");
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log("registers (M; with optional enable/reset), output registers (P; with optional\n");
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log("enable/reset), pre-adder and/or post-adder into Xilinx DSP resources.\n");
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log("Pack input registers (A2, A1, B2, B1, C, D, AD; with optional enable/reset),\n");
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log("pipeline registers (M; with optional enable/reset), output registers (P; with\n");
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log("optional enable/reset), pre-adder and/or post-adder into Xilinx DSP resources.\n");
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log("\n");
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log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
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log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
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log("used to override the existing accumulation result with a new value.\n");
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log("\n");
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log("Use of the dedicated 'PCOUT' -> 'PCIN' path is detected for 'P' -> 'C' connections\n");
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log("where 'P' is right-shifted by 18-bits and used as an input to the post-adder (a\n");
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log("pattern common for summing partial products to implement wide multiplies).\n");
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log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
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log("connections (optionally, where 'P' is right-shifted by 18-bits and used as an\n");
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log("input to the post-adder -- a pattern common for summing partial products to\n");
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log("implement wide multipliers).\n");
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log("\n");
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log("\n");
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log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");
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@ -104,9 +104,9 @@ code sigA sigD
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}
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endcode
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cemux ffA2rstmux ffA2cepol ffArstpol
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cemux ffA2rstmux ffA2cepol ffArstpol ffA1 ffA1cemux ffA1rstmux ffA1cepol
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// Only search for ffA2 if there was a pre-adder
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// (otherwise ffA2 would have been matched as ffA2)
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// (otherwise ffA2 would have been matched as ffAD)
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if (preAdd) {
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if (param(dsp, \AREG).as_int() == 0) {
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argQ = sigA;
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@ -114,11 +114,13 @@ code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cem
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if (dff) {
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ffA2 = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffA2cepol = dffcepol;
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ffArstpol = dffrstpol;
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}
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if (dffcemux) {
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ffA2cemux = dffcemux;
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ffA2rstmux = dffrstmux;
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ffA2cepol = dffcepol;
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ffArstpol = dffrstpol;
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}
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sigA = dffD;
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}
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@ -134,9 +136,37 @@ code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cem
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ffA2cepol = ffADcepol;
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ffArstpol = ffADrstpol;
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}
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// Now attempt to match A1
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if (ffA2) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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if ((ffA2rstmux != nullptr) ^ (dffrstmux != nullptr))
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goto ffA1_end;
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if (dffrstmux) {
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if (ffArstpol != dffrstpol)
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goto ffA1_end;
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if (port(ffA2rstmux, \S) != port(dffrstmux, \S))
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goto ffA1_end;
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ffA1rstmux = dffrstmux;
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}
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ffA1 = dff;
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clock = dffclock;
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if (dffcemux) {
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ffA1cemux = dffcemux;
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ffA1cepol = dffcepol;
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}
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sigA = dffD;
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ffA1_end: ;
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}
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}
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endcode
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code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock
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code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock ffB1 ffB1cemux ffB1rstmux ffB1cepol
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if (param(dsp, \BREG).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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@ -150,6 +180,35 @@ code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock
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ffBrstpol = dffrstpol;
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}
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sigB = dffD;
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// Now attempt to match B1
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if (ffB2) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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if ((ffB2rstmux != nullptr) ^ (dffrstmux != nullptr))
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goto ffB1_end;
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if (dffrstmux) {
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if (ffBrstpol != dffrstpol)
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goto ffB1_end;
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if (port(ffB2rstmux, \S) != port(dffrstmux, \S))
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goto ffB1_end;
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ffB1rstmux = dffrstmux;
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}
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ffB1 = dff;
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clock = dffclock;
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if (dffcemux) {
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ffB1cemux = dffcemux;
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ffB1cepol = dffcepol;
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}
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sigB = dffD;
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ffB1_end: ;
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}
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}
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}
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}
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endcode
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@ -387,6 +446,7 @@ code argD
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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argD = port(ffcemux, ffcepol ? \B : \A);
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dffD.replace(port(ffcemux, \Y), argD);
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}
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else
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