364 commits

Author	SHA1	Message	Date
Eddie Hung	e574edc3e9	Populate generate for xilinx_srl.fixed pattern	2019-08-26 14:21:17 -07:00
Eddie Hung	cf9e017127	Add xilinx_srl_fixed, fix typos	2019-08-26 14:20:06 -07:00
Eddie Hung	7911143827	Create new $__XILINX_SHREG_ cell for variable length too	2019-08-23 18:15:49 -07:00
Eddie Hung	a048fc93e8	Do not allow Q of last cell of variable length SRL to be (* keep *)	2019-08-23 18:15:24 -07:00
Eddie Hung	ee9f6e6243	Also add first.Q to chain_bits since variable length	2019-08-23 18:14:06 -07:00
Eddie Hung	70ce3d0670	Do not enforce !EN_POLARITY on $dffe	2019-08-23 18:11:28 -07:00
Eddie Hung	188b49378a	Create new cell for fixed length SRL	2019-08-23 17:25:30 -07:00
Eddie Hung	e081303ee8	Cleanup FDRE matching	2019-08-23 17:23:52 -07:00
Eddie Hung	54488cfb82	Oops don't need a finally block	2019-08-23 16:39:37 -07:00
Eddie Hung	83e2d87fb8	Keep track of bits in variable length chain, to check for taps	2019-08-23 16:21:10 -07:00
Eddie Hung	f2d4814284	Don't forget $dff has no EN	2019-08-23 16:14:57 -07:00
Eddie Hung	2217d926a9	Same for variable length	2019-08-23 16:13:16 -07:00
Eddie Hung	b1caf7be5e	Filter on en_port for fixed length	2019-08-23 16:09:46 -07:00
Eddie Hung	513af10d77	Check clock is consistent	2019-08-23 15:18:26 -07:00
Eddie Hung	c762618783	Fix last_cell.D	2019-08-23 15:08:49 -07:00
Eddie Hung	ca5de78e76	Revert "Add a unique argument to pmgen's nusers()" ... This reverts commit 1d88887cfd.	2019-08-23 15:04:00 -07:00
Eddie Hung	e85e6e8d45	Revert "Fix polarity" ... This reverts commit 9cd23cf0fe.	2019-08-23 15:03:42 -07:00
Eddie Hung	9cd23cf0fe	Fix polarity	2019-08-23 14:49:34 -07:00
Eddie Hung	c2757613b6	Check for non unique nusers/fanouts	2019-08-23 14:32:36 -07:00
Eddie Hung	1d88887cfd	Add a unique argument to pmgen's nusers()	2019-08-23 14:32:17 -07:00
Eddie Hung	8ecfd55d5a	Update doc	2019-08-23 14:16:41 -07:00
Eddie Hung	3d7f4aa0c8	Remove (* init *) entry when consumed into SRL	2019-08-23 13:56:01 -07:00
Eddie Hung	967a36c125	indo -> into	2019-08-23 13:16:50 -07:00
Eddie Hung	a1f78eab04	indo -> into	2019-08-23 13:15:41 -07:00
Eddie Hung	5939ffdc07	Forgot to slice	2019-08-23 13:06:59 -07:00
Eddie Hung	242b3083ea	Cope with possibility that D could connect to Q on same cell	2019-08-23 13:06:31 -07:00
Eddie Hung	18b64609c2	xilinx_srl to use 'slice' features of pmgen for word level	2019-08-23 12:22:06 -07:00
Eddie Hung	f4fd41d5d2	Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl	2019-08-23 11:35:06 -07:00
Clifford Wolf	55bf8f69e0	Fix port hanlding in pmgen ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-23 16:26:54 +02:00
Clifford Wolf	adb81ba386	Add pmgen slices and choices ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-23 16:15:50 +02:00
Eddie Hung	6e8fda8bf0	Add doc	2019-08-22 11:52:24 -07:00
Eddie Hung	cabadb85e2	Add copyright	2019-08-22 11:25:19 -07:00
Eddie Hung	9f3ed1726e	pmgen to also iterate over all module ports	2019-08-22 11:15:16 -07:00
Eddie Hung	74bd190d3b	Remove output_bits	2019-08-22 11:14:59 -07:00
Eddie Hung	231ddbf95c	Forgot to set ud_variable.minlen	2019-08-22 11:02:17 -07:00
Eddie Hung	61639d5387	Do not run xilinx_srl_pm in fixed loop	2019-08-22 10:51:04 -07:00
Eddie Hung	d0b2973413	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-22 10:32:06 -07:00
Eddie Hung	7d02d17b16	Reuse var	2019-08-21 19:18:40 -07:00
Eddie Hung	5c8344363f	Revert "Trim shiftx_width when upper bits are 1'bx" ... This reverts commit 7e7965ca7b.	2019-08-21 19:18:27 -07:00
Eddie Hung	7e7965ca7b	Trim shiftx_width when upper bits are 1'bx	2019-08-21 18:43:17 -07:00
Eddie Hung	ed7be3e6b6	Add comment	2019-08-21 17:36:38 -07:00
Eddie Hung	15188033da	Add variable length support to xilinx_srl	2019-08-21 17:34:40 -07:00
Eddie Hung	6d76ae4c65	Rename pattern to fixed	2019-08-21 15:46:58 -07:00
Eddie Hung	b0a3b430bf	attribute -> attr	2019-08-21 15:44:07 -07:00
Eddie Hung	61b4d7ae13	Use Cell::has_keep_attribute()	2019-08-21 15:41:46 -07:00
Eddie Hung	6fa9e03e4c	xilinx_srl to support FDRE and FDRE_1	2019-08-21 15:35:29 -07:00
Eddie Hung	3c8e8521a6	Fix polarity of EN_POL	2019-08-21 14:42:11 -07:00
Eddie Hung	a980f0d4be	Add CLKPOL == 0	2019-08-21 14:35:40 -07:00
Eddie Hung	1c7d721558	Reject if not minlen from inside pattern matcher	2019-08-21 14:26:24 -07:00
Eddie Hung	cab2bd083e	Get wire via SigBit	2019-08-21 13:47:47 -07:00