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https://github.com/YosysHQ/yosys
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WIP for xiinx_dsp_cascadeAB
This commit is contained in:
Eddie Hung
parent
b0ad2592be
commit
0bca366bcd
1 changed files with 499 additions and 3 deletions
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@ -1,4 +1,4 @@
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pattern xilinx_dsp_cascade
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pattern xilinx_dsp_cascadeP
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigSpec> sigC
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@ -33,7 +33,7 @@ match dsp_pcout
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select nusers(port(dsp_pcout, \P, SigSpec())) > 1
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select nusers(port(dsp_pcout, \PCOUT, SigSpec())) <= 1
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index <SigSpec> port(dsp_pcout, \P)[0] === sigC[0]
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index <SigBit> port(dsp_pcout, \P)[0] === sigC[0]
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filter GetSize(port(dsp_pcin, \P)) >= GetSize(sigC)
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filter port(dsp_pcout, \P).extract(0, GetSize(sigC)) == sigC
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@ -46,7 +46,7 @@ match dsp_pcout_shift17
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select nusers(port(dsp_pcout_shift17, \P, SigSpec())) > 1
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select nusers(port(dsp_pcout_shift17, \PCOUT, SigSpec())) <= 1
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index <SigSpec> port(dsp_pcout_shift17, \P)[17] === sigC[0]
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index <SigBit> port(dsp_pcout_shift17, \P)[17] === sigC[0]
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filter GetSize(port(dsp_pcout_shift17, \P)) >= GetSize(sigC)+17
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filter port(dsp_pcout_shift17, \P).extract(17, GetSize(sigC)) == sigC
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endmatch
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@ -90,5 +90,501 @@ code
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blacklist(dsp_pcout);
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}
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did_something = true;
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accept;
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endcode
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// ##########
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pattern xilinx_dsp_cascadeAB
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigB
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state <bool> ffA1cepol ffA2cepol ffB1cepol ffB2cepol
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state <bool> ffArstpol ffBrstpol
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state <Cell*> ffA1 ffA1cemux ffA1rstmux ffA2 ffA2cemux ffA2rstmux
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state <Cell*> ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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code
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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endcode
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match dspD
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select dspD->type.in(\DSP48E1)
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select (param(dspD, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT" && nusers(port(dspD, \A, SigSpec())) > 1 && nusers(port(dspD, \ACIN, SigSpec())) == 0) || (param(dspD, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT" && nusers(port(dspD, \B, SigSpec())) > 1 && nusers(port(dspD, \BCIN, SigSpec())) == 0)
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endmatch
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code sigA sigB
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if (param(dspD, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT")
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sigA = unextend(port(dspD, \A));
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if (param(dspD, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT")
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sigB = unextend(port(dspD, \B));
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endcode
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code argQ ffA2 ffA2cemux ffA2rstmux ffA2cepol ffArstpol ffA1 ffA1cemux ffA1rstmux ffA1cepol sigA clock
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if (!sigA.empty()) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffA2 = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffA2rstmux = dffrstmux;
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ffArstpol = dffrstpol;
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}
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if (dffcemux) {
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ffA2cemux = dffcemux;
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ffA2cepol = dffcepol;
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}
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sigA = dffD;
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// Now attempt to match A1
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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if ((ffA2rstmux != nullptr) ^ (dffrstmux != nullptr))
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goto reject_ffA1;
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if (dffrstmux) {
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if (ffArstpol != dffrstpol)
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goto reject_ffA1;
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if (port(ffA2rstmux, \S) != port(dffrstmux, \S))
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goto reject_ffA1;
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ffA1rstmux = dffrstmux;
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}
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ffA1 = dff;
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clock = dffclock;
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if (dffcemux) {
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ffA1cemux = dffcemux;
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ffA1cepol = dffcepol;
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}
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sigA = dffD;
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reject_ffA1: ;
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}
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}
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}
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endcode
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match dspQA2
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if ffA1
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select dspQA2->type.in(\DSP48E1)
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select param(dspQA2, \A_REG, 2).as_int() == 2
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select nusers(port(dspQA2, \A, SigSpec())) > 1
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select nusers(port(dspQA2, \ACOUT, SigSpec())) == 0
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slice offset GetSize(port(dspQA2, \A))
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index <SigBit> port(dspQA2, \A)[offset] === sigA[0]
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index <SigBit> port(dspQA2, \CLK) === port(dspD, \CLK)
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// Check that the rest of sigA is present
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filter GetSize(port(dspQA2, \A)) >= offset + GetSize(sigA)
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filter port(dspQA2, \A).extract(offset, GetSize(sigA)) == sigA
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optional
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endmatch
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code
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if (dspQA2) {
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// Check CE and RST are compatible
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if ((ffA1cemux != nullptr) == port(dspQA2, \CEA1, State::S1).is_fully_const())
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reject;
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if ((ffA2cemux != nullptr) == port(dspQA2, \CEA2, State::S1).is_fully_const())
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reject;
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if ((ffA1rstmux != nullptr) == port(dspQA2, \RSTA, State::S0).is_fully_const())
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reject;
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if ((ffA2rstmux != nullptr) == port(dspQA2, \RSTA, State::S0).is_fully_const())
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reject;
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if (ffA1cemux) {
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if (port(dspQA2, \CEA1) != port(ffA1cemux, \S))
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reject;
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// TODO: Support inversions
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if (!ffA1cepol)
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reject;
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}
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if (ffA2cemux) {
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if (port(dspQA2, \CEA2) != port(ffA2cemux, \S))
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reject;
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// TODO: Support inversions
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if (!ffA2cepol)
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reject;
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}
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if (ffA1rstmux) {
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if (port(dspQA2, \RSTA) != port(ffA1rstmux, \S))
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reject;
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// TODO: Support inversions
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if (!ffArstpol)
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reject;
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}
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if (ffA2rstmux) {
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if (port(dspQA2, \RSTA) != port(ffA2rstmux, \S))
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reject;
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// TODO: Support inversions
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if (!ffArstpol)
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reject;
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}
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}
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endcode
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match dspQA1
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if !dspQA1 && !ffA1
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if ffA2
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select dspQA1->type.in(\DSP48E1)
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select param(dspQA1, \A_REG, 2).as_int() == 1
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select nusers(port(dspQA1, \A, SigSpec())) > 1
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select nusers(port(dspQA1, \ACOUT, SigSpec())) == 0
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slice offset GetSize(port(dspQA1, \A))
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index <SigBit> port(dspQA1, \A)[offset] === sigA[0]
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index <SigBit> port(dspQA1, \CLK) === port(dspD, \CLK)
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// Check that the rest of sigA is present
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filter GetSize(port(dspQA1, \A)) >= offset + GetSize(sigA)
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filter port(dspQA1, \A).extract(offset, GetSize(sigA)) == sigA
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optional
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endmatch
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code
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if (dspQA1) {
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// Check CE and RST are compatible
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if ((ffA2cemux != NULL) == port(dspQA1, \CEA2, State::S1).is_fully_const())
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reject;
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if ((ffA2rstmux != NULL) == port(dspQA1, \RSTA, State::S0).is_fully_const())
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reject;
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if (!ffA2cepol || !ffArstpol)
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reject;
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if (ffA2cemux) {
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if (port(dspQA1, \CEA2) != port(ffA2cemux, \S))
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reject;
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// TODO: Support inversions
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if (!ffA2cepol)
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reject;
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}
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if (ffA2rstmux) {
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if (port(dspQA1, \RSTA) != port(ffA2rstmux, \S))
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reject;
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// TODO: Support inversions
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if (!ffArstpol)
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reject;
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}
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}
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endcode
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code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol ffB1 ffB1cemux ffB1rstmux ffB1cepol sigB clock
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if (!sigB.empty()) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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ffB2 = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffB2rstmux = dffrstmux;
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ffBrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffB2cemux = dffcemux;
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ffB2cepol = dffcepol;
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}
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sigB = dffD;
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// Now attempt to match B1
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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if ((ffB2rstmux != nullptr) ^ (dffrstmux != nullptr))
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goto reject_ffB1;
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if (dffrstmux) {
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if (ffBrstpol != dffrstpol)
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goto reject_ffB1;
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if (port(ffB2rstmux, \S) != port(dffrstmux, \S))
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goto reject_ffB1;
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ffB1rstmux = dffrstmux;
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}
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ffB1 = dff;
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clock = dffclock;
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if (dffcemux) {
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ffB1cemux = dffcemux;
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ffB1cepol = dffcepol;
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}
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sigB = dffD;
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reject_ffB1: ;
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}
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}
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}
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endcode
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match dspQB2
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if ffB1
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select dspQB2->type.in(\DSP48E1)
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select param(dspQB2, \B_REG, 2).as_int() == 2
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select nusers(port(dspQB2, \B, SigSpec())) > 1
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select nusers(port(dspQB2, \BCOUT, SigSpec())) == 0
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slice offset GetSize(port(dspQB2, \B))
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index <SigBit> port(dspQB2, \B)[offset] === sigB[0]
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index <SigBit> port(dspQB2, \CLK) === port(dspD, \CLK)
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// Check that the rest of sigB is present
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filter GetSize(port(dspQB2, \B)) >= offset + GetSize(sigB)
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filter port(dspQB2, \B).extract(offset, GetSize(sigB)) == sigB
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optional
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endmatch
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code
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if (dspQB2) {
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// Check CE and RST are compatible
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if ((ffB1cemux != nullptr) == port(dspQB2, \CEB1, State::S1).is_fully_const())
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reject;
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if ((ffB2cemux != NULL) == port(dspQB2, \CEB2, State::S1).is_fully_const())
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reject;
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if ((ffB1rstmux != NULL) == port(dspQB2, \RSTB, State::S0).is_fully_const())
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reject;
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if ((ffB2rstmux != NULL) == port(dspQB2, \RSTB, State::S0).is_fully_const())
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reject;
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if (ffB1cemux) {
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if (port(dspQB2, \CEB1) != port(ffB1cemux, \S))
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reject;
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// TODO: Support inversions
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if (!ffB1cepol)
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reject;
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}
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if (ffB2cemux) {
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if (port(dspQB2, \CEB2) != port(ffB2cemux, \S))
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reject;
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// TODO: Support inversions
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if (!ffB2cepol)
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reject;
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}
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if (ffB2rstmux) {
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if (port(dspQB2, \RSTB) != port(ffB2rstmux, \S))
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reject;
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// TODO: Support inversions
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if (!ffBrstpol)
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reject;
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}
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}
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endcode
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match dspQB1
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if !dspQB1 && !ffB1
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if ffB2
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select dspQB1->type.in(\DSP48E1)
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select param(dspQB1, \B_REG, 2).as_int() >= 1
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select nusers(port(dspQB1, \B, SigSpec())) > 1
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select nusers(port(dspQB1, \BCOUT, SigSpec())) == 0
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slice offset GetSize(port(dspQB1, \B))
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index <SigBit> port(dspQB1, \B)[offset] === sigB[0]
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index <SigBit> port(dspQB1, \CLK) === port(dspD, \CLK)
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// Check that the rest of sigB is present
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filter GetSize(port(dspQB1, \B)) >= offset + GetSize(sigB)
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filter port(dspQB1, \B).extract(offset, GetSize(sigB)) == sigB
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optional
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endmatch
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code
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if (dspQB1) {
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// Check CE and RST are compatible
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if ((ffB2cemux != NULL) != port(dspQB1, \CEB2, State::S1).is_fully_const())
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reject;
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if ((ffB2rstmux != NULL) != port(dspQB1, \RSTB, State::S0).is_fully_const())
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reject;
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if (!ffA2cepol || !ffArstpol)
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reject;
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if (ffA2cemux) {
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if (port(dspQB1, \CEB2) != port(ffB2cemux, \S))
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reject;
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// TODO: Support inversions
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if (!ffA2cepol)
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reject;
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}
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if (ffA2rstmux) {
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if (port(dspQB1, \RSTB) != port(ffB2rstmux, \S))
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reject;
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// TODO: Support inversions
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if (!ffArstpol)
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reject;
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}
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}
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endcode
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code
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if (dspQA1 || dspQA2) {
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dspD->setParam(\A_INPUT, Const("CASCADE"));
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dspD->setPort(\A, Const(0, 30));
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Wire *cascade = module->addWire(NEW_ID, 30);
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if (dspQA1) {
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dspQA1->setParam(\ACASCREG, 1);
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dspQA1->setPort(\ACOUT, cascade);
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log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dspQA1), log_id(dspD));
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}
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else if (dspQA2) {
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dspQA2->setParam(\ACASCREG, 2);
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dspQA2->setPort(\ACOUT, cascade);
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log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dspQA2), log_id(dspD));
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}
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else
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log_abort();
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dspD->setPort(\ACIN, cascade);
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did_something = true;
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}
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if (dspQB1 || dspQB2) {
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dspD->setParam(\B_INPUT, Const("CASCADE"));
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dspD->setPort(\B, Const(0, 18));
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Wire *cascade = module->addWire(NEW_ID, 18);
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if (dspQB1) {
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dspQB1->setParam(\BCASCREG, 1);
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dspQB1->setPort(\BCOUT, cascade);
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log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dspQB1), log_id(dspD));
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}
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else if (dspQB2) {
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dspQB2->setParam(\BCASCREG, 2);
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dspQB2->setPort(\BCOUT, cascade);
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log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dspQB2), log_id(dspD));
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}
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else
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log_abort();
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dspD->setPort(\BCIN, cascade);
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did_something = true;
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}
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accept;
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endcode
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// #######################
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subpattern in_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argQ.chunks()) {
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if (!c.wire)
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reject;
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if (c.wire->get_bool_attribute(\keep))
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reject;
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}
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endcode
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match ff
|
||||
select ff->type.in($dff)
|
||||
// DSP48E1 does not support clock inversion
|
||||
select param(ff, \CLK_POLARITY).as_bool()
|
||||
|
||||
slice offset GetSize(port(ff, \D))
|
||||
index <SigBit> port(ff, \Q)[offset] === argQ[0]
|
||||
|
||||
// Check that the rest of argQ is present
|
||||
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
|
||||
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
|
||||
|
||||
set ffoffset offset
|
||||
endmatch
|
||||
|
||||
code argQ argD
|
||||
{
|
||||
if (clock != SigBit() && port(ff, \CLK) != clock)
|
||||
reject;
|
||||
|
||||
SigSpec Q = port(ff, \Q);
|
||||
dff = ff;
|
||||
dffclock = port(ff, \CLK);
|
||||
dffD = argQ;
|
||||
argD = port(ff, \D);
|
||||
argQ = Q;
|
||||
dffD.replace(argQ, argD);
|
||||
// Only search for ffrstmux if dffD only
|
||||
// has two (ff, ffrstmux) users
|
||||
if (nusers(dffD) > 2)
|
||||
argD = SigSpec();
|
||||
}
|
||||
endcode
|
||||
|
||||
match ffrstmux
|
||||
if !argD.empty()
|
||||
select ffrstmux->type.in($mux)
|
||||
index <SigSpec> port(ffrstmux, \Y) === argD
|
||||
|
||||
choice <IdString> BA {\B, \A}
|
||||
// DSP48E1 only supports reset to zero
|
||||
select port(ffrstmux, BA).is_fully_zero()
|
||||
|
||||
define <bool> pol (BA == \B)
|
||||
set ffrstpol pol
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argD
|
||||
if (ffrstmux) {
|
||||
dffrstmux = ffrstmux;
|
||||
dffrstpol = ffrstpol;
|
||||
argD = port(ffrstmux, ffrstpol ? \A : \B);
|
||||
dffD.replace(port(ffrstmux, \Y), argD);
|
||||
|
||||
// Only search for ffcemux if argQ has at
|
||||
// least 3 users (ff, <upstream>, ffrstmux) and
|
||||
// dffD only has two (ff, ffrstmux)
|
||||
if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
|
||||
argD = SigSpec();
|
||||
}
|
||||
else
|
||||
dffrstmux = nullptr;
|
||||
endcode
|
||||
|
||||
match ffcemux
|
||||
if !argD.empty()
|
||||
select ffcemux->type.in($mux)
|
||||
index <SigSpec> port(ffcemux, \Y) === argD
|
||||
choice <IdString> AB {\A, \B}
|
||||
index <SigSpec> port(ffcemux, AB) === argQ
|
||||
define <bool> pol (AB == \A)
|
||||
set ffcepol pol
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argD
|
||||
if (ffcemux) {
|
||||
dffcemux = ffcemux;
|
||||
dffcepol = ffcepol;
|
||||
argD = port(ffcemux, ffcepol ? \B : \A);
|
||||
dffD.replace(port(ffcemux, \Y), argD);
|
||||
}
|
||||
else
|
||||
dffcemux = nullptr;
|
||||
endcode
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue