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https://github.com/YosysHQ/yosys
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Refactor ce{mux,pol} -> hold{mux,pol}
This commit is contained in:
Eddie Hung
parent
429c9852ce
commit
1a0f7ed09c
2 changed files with 77 additions and 77 deletions
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@ -31,15 +31,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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#if 1
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log("\n");
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log("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
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log("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
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log("ffCD: %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDcemux, "--"));
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log("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAholdmux, "--"), log_id(st.ffArstmux, "--"));
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log("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBholdmux, "--"), log_id(st.ffBrstmux, "--"));
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log("ffCD: %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDholdmux, "--"));
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log("mul: %s\n", log_id(st.mul, "--"));
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log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
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log("ffH: %s\n", log_id(st.ffH, "--"));
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log("add: %s\n", log_id(st.add, "--"));
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log("mux: %s\n", log_id(st.mux, "--"));
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log("ffO: %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOcemux, "--"), log_id(st.ffOrstmux, "--"));
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log("ffO: %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOholdmux, "--"), log_id(st.ffOrstmux, "--"));
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#endif
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log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
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@ -99,16 +99,16 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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cell->setParam("\\D_REG", st.ffCD ? State::S1 : State::S0);
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SigSpec AHOLD, BHOLD, CDHOLD;
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if (st.ffAcemux)
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AHOLD = st.ffAcepol ? pm.module->Not(NEW_ID, st.ffAcemux->getPort("\\S")) : st.ffAcemux->getPort("\\S");
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if (st.ffAholdmux)
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AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffAholdmux->getPort("\\S"));
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else
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AHOLD = State::S0;
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if (st.ffBcemux)
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BHOLD = st.ffBcepol ? pm.module->Not(NEW_ID, st.ffBcemux->getPort("\\S")) : st.ffBcemux->getPort("\\S");
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if (st.ffBholdmux)
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BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffBholdmux->getPort("\\S"));
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else
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BHOLD = State::S0;
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if (st.ffCDcemux)
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CDHOLD = st.ffCDcepol ? pm.module->Not(NEW_ID, st.ffCDcemux->getPort("\\S")) : st.ffCDcemux->getPort("\\S");
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if (st.ffCDholdmux)
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CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort("\\S"));
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else
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CDHOLD = State::S0;
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cell->setPort("\\AHOLD", AHOLD);
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@ -210,8 +210,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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}
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SigSpec OHOLD;
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if (st.ffOcemux)
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OHOLD = st.ffOcemux ? pm.module->Not(NEW_ID, st.ffOcemux->getPort("\\S")) : st.ffOcemux->getPort("\\S");
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if (st.ffOholdmux)
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OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOholdmux->getPort("\\S"));
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else
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OHOLD = State::S0;
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cell->setPort("\\OHOLDTOP", OHOLD);
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@ -219,7 +219,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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SigSpec ORST;
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if (st.ffOrstmux)
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ORST = st.ffOrstmux ? st.ffOrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOrstmux->getPort("\\S"));
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ORST = st.ffOrstpol ? st.ffOrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOrstmux->getPort("\\S"));
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else
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ORST = State::S0;
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cell->setPort("\\ORSTTOP", ORST);
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@ -6,20 +6,20 @@ state <SigSpec> sigA sigB sigCD sigH sigO
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state <Cell*> add mux
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state <IdString> addAB muxAB
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state <bool> ffAcepol ffBcepol ffCDcepol ffOcepol
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state <bool> ffAholdpol ffBholdpol ffCDholdpol ffOholdpol
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state <bool> ffArstpol ffBrstpol ffCDrstpol ffOrstpol
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state <Cell*> ffA ffAcemux ffArstmux ffB ffBcemux ffBrstmux ffCD ffCDcemux
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state <Cell*> ffFJKG ffH ffO ffOcemux ffOrstmux
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state <Cell*> ffA ffAholdmux ffArstmux ffB ffBholdmux ffBrstmux ffCD ffCDholdmux
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state <Cell*> ffFJKG ffH ffO ffOholdmux ffOrstmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <bool> ffholdpol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol dffclock_pol
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udata <Cell*> dff dffholdmux dffrstmux
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udata <bool> dffholdpol dffrstpol dffclock_pol
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match mul
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select mul->type.in($mul, \SB_MAC16)
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@ -63,7 +63,7 @@ code sigA sigB sigH
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log_assert(nusers(O.extract_end(i)) <= 1);
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endcode
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code argQ ffA ffAcemux ffArstmux ffAcepol ffArstpol sigA clock clock_pol
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code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
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if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
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argQ = sigA;
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subpattern(in_dffe);
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@ -75,16 +75,16 @@ code argQ ffA ffAcemux ffArstmux ffAcepol ffArstpol sigA clock clock_pol
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ffArstmux = dffrstmux;
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ffArstpol = dffrstpol;
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}
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if (dffcemux) {
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ffAcemux = dffcemux;
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ffAcepol = dffcepol;
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if (dffholdmux) {
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ffAholdmux = dffholdmux;
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ffAholdpol = dffholdpol;
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}
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sigA = dffD;
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}
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}
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endcode
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code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock clock_pol
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code argQ ffB ffBholdmux ffBrstmux ffBholdpol ffBrstpol sigB clock clock_pol
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if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
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argQ = sigB;
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subpattern(in_dffe);
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@ -96,9 +96,9 @@ code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock clock_pol
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ffBrstmux = dffrstmux;
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ffBrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffBcemux = dffcemux;
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ffBcepol = dffcepol;
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if (dffholdmux) {
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ffBholdmux = dffholdmux;
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ffBholdpol = dffholdpol;
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}
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sigB = dffD;
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}
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@ -113,7 +113,7 @@ code argD ffFJKG sigH sigO clock clock_pol
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subpattern(out_dffe);
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if (dff) {
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// F/J/K/G do not have a CE-like (hold) input
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if (dffcemux)
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if (dffholdmux)
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goto reject_ffFJKG;
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// Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
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@ -154,7 +154,7 @@ code argD ffH sigH sigO clock clock_pol
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subpattern(out_dffe);
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if (dff) {
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// H does not have a CE-like (hold) input
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if (dffcemux)
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if (dffholdmux)
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goto reject_ffH;
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// Reset signal of H (IRSTBOT) shared with B
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@ -226,7 +226,7 @@ code sigO
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sigO = port(mux, \Y);
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endcode
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code argD ffO ffOcemux ffOrstmux ffOcepol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
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code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
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if (mul->type != \SB_MAC16 ||
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// Ensure that register is not already used
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((mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1) &&
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@ -258,9 +258,9 @@ code argD ffO ffOcemux ffOrstmux ffOcepol ffOrstpol sigO sigCD clock clock_pol c
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ffOrstmux = dffrstmux;
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ffOrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffOcemux = dffcemux;
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ffOcepol = dffcepol;
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if (dffholdmux) {
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ffOholdmux = dffholdmux;
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ffOholdpol = dffholdpol;
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}
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sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
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@ -278,15 +278,15 @@ code argD ffO ffOcemux ffOrstmux ffOcepol ffOrstpol sigO sigCD clock clock_pol c
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}
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endcode
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code argQ ffCD ffCDcemux ffCDcepol ffCDrstpol sigCD clock clock_pol
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code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
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if (!sigCD.empty() &&
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(mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
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argQ = sigCD;
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subpattern(in_dffe);
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if (dff) {
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if (dffcemux) {
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ffCDcemux = dffcemux;
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ffCDcepol = dffcepol;
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if (dffholdmux) {
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ffCDholdmux = dffholdmux;
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ffCDholdpol = dffholdpol;
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}
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// Reset signal of C (IRSTTOP) and D (IRSTBOT)
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@ -403,7 +403,7 @@ code argD
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argD = port(ffrstmux, ffrstpol ? \A : \B);
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dffD.replace(port(ffrstmux, \Y), argD);
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// Only search for ffcemux if argQ has at
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// Only search for ffholdmux if argQ has at
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// least 3 users (ff, <upstream>, ffrstmux) and
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// dffD only has two (ff, ffrstmux)
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if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
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@ -413,26 +413,26 @@ code argD
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dffrstmux = nullptr;
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endcode
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match ffcemux
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match ffholdmux
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if !argD.empty()
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select ffcemux->type.in($mux)
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index <SigSpec> port(ffcemux, \Y) === argD
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(ffcemux, AB) === argQ
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define <bool> pol (AB == \A)
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set ffcepol pol
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select ffholdmux->type.in($mux)
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index <SigSpec> port(ffholdmux, \Y) === argD
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choice <IdString> BA {\B, \A}
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index <SigSpec> port(ffholdmux, BA) === argQ
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define <bool> pol (BA == \B)
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set ffholdpol pol
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semioptional
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endmatch
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code argD
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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argD = port(ffcemux, ffcepol ? \B : \A);
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dffD.replace(port(ffcemux, \Y), argD);
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if (ffholdmux) {
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dffholdmux = ffholdmux;
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dffholdpol = ffholdpol;
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argD = port(ffholdmux, ffholdpol ? \A : \B);
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dffD.replace(port(ffholdmux, \Y), argD);
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}
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else
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dffcemux = nullptr;
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dffholdmux = nullptr;
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endcode
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// #######################
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@ -447,41 +447,41 @@ code
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reject;
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endcode
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match ffcemux
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select ffcemux->type.in($mux)
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// ffcemux output must have two users: ffcemux and ff.D
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select nusers(port(ffcemux, \Y)) == 2
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match ffholdmux
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select ffholdmux->type.in($mux)
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// ffholdmux output must have two users: ffholdmux and ff.D
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select nusers(port(ffholdmux, \Y)) == 2
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choice <IdString> AB {\A, \B}
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// keep-last-value net must have at least three users: ffcemux, ff, downstream sink(s)
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select nusers(port(ffcemux, AB)) >= 3
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choice <IdString> BA {\B, \A}
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// keep-last-value net must have at least three users: ffholdmux, ff, downstream sink(s)
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select nusers(port(ffholdmux, BA)) >= 3
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slice offset GetSize(port(ffcemux, \Y))
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigBit> port(ffcemux, BA)[offset] === argD[0]
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slice offset GetSize(port(ffholdmux, \Y))
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define <IdString> AB (BA == \B ? \A : \B)
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index <SigBit> port(ffholdmux, AB)[offset] === argD[0]
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// Check that the rest of argD is present
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filter GetSize(port(ffcemux, BA)) >= offset + GetSize(argD)
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filter port(ffcemux, BA).extract(offset, GetSize(argD)) == argD
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filter GetSize(port(ffholdmux, AB)) >= offset + GetSize(argD)
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filter port(ffholdmux, AB).extract(offset, GetSize(argD)) == argD
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set ffoffset offset
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define <bool> pol (BA == \B)
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set ffcepol pol
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set ffholdpol pol
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semioptional
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endmatch
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code argD argQ
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dffcemux = ffcemux;
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if (ffcemux) {
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SigSpec BA = port(ffcemux, ffcepol ? \B : \A);
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SigSpec Y = port(ffcemux, \Y);
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dffholdmux = ffholdmux;
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if (ffholdmux) {
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SigSpec AB = port(ffholdmux, ffholdpol ? \A : \B);
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SigSpec Y = port(ffholdmux, \Y);
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argQ = argD;
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argD.replace(BA, Y);
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argQ.replace(BA, port(ffcemux, ffcepol ? \A : \B));
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argD.replace(AB, Y);
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argQ.replace(AB, port(ffholdmux, ffholdpol ? \B : \A));
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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dffholdmux = ffholdmux;
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dffholdpol = ffholdpol;
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}
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endcode
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@ -499,7 +499,7 @@ match ffrstmux
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index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
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// Check that offset is consistent
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filter !ffcemux || ffoffset == offset
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filter !ffholdmux || ffoffset == offset
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// Check that the rest of argD is present
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filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
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filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
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@ -532,12 +532,12 @@ match ff
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index <SigBit> port(ff, \D)[offset] === argD[0]
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// Check that offset is consistent
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filter (!ffcemux && !ffrstmux) || ffoffset == offset
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filter (!ffholdmux && !ffrstmux) || ffoffset == offset
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// Check that the rest of argD is present
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filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
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filter port(ff, \D).extract(offset, GetSize(argD)) == argD
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// Check that FF.Q is connected to CE-mux
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filter !ffcemux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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filter !ffholdmux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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set ffoffset offset
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endmatch
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@ -552,7 +552,7 @@ code argQ
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}
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SigSpec D = port(ff, \D);
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SigSpec Q = port(ff, \Q);
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if (!ffcemux) {
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if (!ffholdmux) {
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argQ = argD;
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argQ.replace(D, Q);
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}
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@ -569,6 +569,6 @@ code argQ
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dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
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}
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// No enable/reset mux possible without flop
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else if (dffcemux || dffrstmux)
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else if (dffholdmux || dffrstmux)
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reject;
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endcode
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