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4565 commits

Author SHA1 Message Date
Miodrag Milanovic
fd3f08753a Fix handling of ce_over_srst 2022-02-21 16:36:12 +01:00
Claire Xenia Wolf
1aa9ad25d0 Fix cycle 0 in aiger witness co-simulation 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-18 16:27:41 +01:00
Miodrag Milanovic
41754b4207 Added AIGER witness file co simulation 2022-02-18 15:04:02 +01:00
Miodrag Milanovic
13a5c28459 simplify logic of handling flip-flops and latches 2022-02-18 09:17:36 +01:00
Miodrag Milanovic
61752b255f Review cleanup 2022-02-17 17:18:36 +01:00
Miodrag Milanovic
fb22d7cdc4 Add support for various ff/latch cells simulation 2022-02-16 13:27:59 +01:00
Claire Xen
49545c73f7
Merge branch 'master' into clk2ff-better-names 2022-02-11 16:03:12 +01:00
Claire Xen
e016518866
Merge pull request #2019 from boqwxp/glift 
Add `glift` command for creating gate-level information flow tracking models and optimization problems
 2022-02-11 15:51:24 +01:00
bfg86
7ac98d1c87 Add -suffix option to rename -wire. 
See #3195
 2022-02-11 00:05:13 +01:00
Lofty
5ac32ea68c abc9: add flow3mfs script 2022-02-10 18:28:35 +00:00
Miodrag Milanović
d7f7227ce8
Merge pull request #3185 from YosysHQ/micko/co_sim 
Add co-simulation in sim pass
 2022-02-07 16:36:43 +01:00
Miodrag Milanovic
c0a156bcb4 Error detection for co-simulation 2022-02-04 11:11:36 +01:00
Miodrag Milanovic
6db23de7b1 bug fix and cleanups 2022-02-04 10:01:06 +01:00
YRabbit
f5609d52c4 Correct a typo in the manual 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-02-02 21:14:38 +10:00
Miodrag Milanovic
990aee5531 respect hide_internal flag 2022-02-02 10:15:22 +01:00
Miodrag Milanovic
169ffcd2fb unify cycles counting and cleanup 2022-02-02 10:08:23 +01:00
Miodrag Milanovic
820b2fdd65 added stimulus mode and param check 2022-02-02 09:37:32 +01:00
Scott Thibault
0a6e2bd5d5 Update comment 2022-02-02 03:21:09 +01:00
Scott Thibault
e04ac4e9e9 Fix unextend method for signed constants 2022-02-02 03:21:09 +01:00
Miodrag Milanovic
8ba2000a50 error when no signal found 2022-01-31 17:41:50 +01:00
Miodrag Milanovic
1b5ff92e62 Cleanup 2022-01-31 13:45:28 +01:00
Miodrag Milanovic
eabd0ff115 Compare bits when not all are defined 2022-01-31 13:41:02 +01:00
Miodrag Milanovic
26de52fa09 Cleanup 2022-01-31 12:00:15 +01:00
Miodrag Milanovic
6513300db7 message update 2022-01-31 11:41:52 +01:00
Miodrag Milanovic
543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Miodrag Milanovic
a6959d30df Use edges when explicit 2022-01-31 09:38:25 +01:00
Miodrag Milanovic
cbadfa0268 Updating initial state and checks 2022-01-31 09:19:34 +01:00
Miodrag Milanovic
190e44f0da Fix scope 2022-01-31 08:56:29 +01:00
Marcelina Kościelnicka
07a657fb0c opt_reduce: Add $bmux and $demux optimization patterns. 2022-01-30 03:37:52 +01:00
Marcelina Kościelnicka
93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Miodrag Milanovic
f04d1398e5 check if stop before start 2022-01-28 19:41:43 +01:00
Miodrag Milanovic
ecbba625c4 set initial state, only flip-flops 2022-01-28 15:59:13 +01:00
Miodrag Milanovic
cb12b7c4d8 ignore not found private signals 2022-01-28 14:20:16 +01:00
Miodrag Milanovic
81b76155d6 recursive check 2022-01-28 13:24:38 +01:00
Miodrag Milanovic
4f75a2ca1b Do actual compare 2022-01-28 12:50:41 +01:00
Miodrag Milanovic
3e35de2be1 Add more options and time handling 2022-01-28 10:18:02 +01:00
Marcelina Kościelnicka
db33b1e535 opt_dff: Don't mutate muxes while ModWalker is active. 2022-01-28 08:55:56 +01:00
Marcelina Kościelnicka
1759c80a3f memory_bram: Make use of new mem emulation functions to map more RAMs. 2022-01-27 19:31:27 +01:00
Miodrag Milanovic
40018e191b Display values of outputs 2022-01-26 16:52:36 +01:00
Miodrag Milanovic
be7be63fec Check if stimulated 2022-01-26 15:51:43 +01:00
Miodrag Milanovic
9a8939f0a4 Read fst and use data to set inputs 2022-01-26 15:50:38 +01:00
Miodrag Milanovic
ccfc00705a Add ability to write to FST file 2022-01-26 09:26:19 +01:00
Austin Seipp
b022fe61a7 opt_dff: fix sequence point copy paste bug 
Newer GCCs emit the following warning for opt_dff:

    passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point]
      560 |      ff.has_clk = ff.has_ce = ff.has_clk = false;
          |      ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Which is correct: the order of whether the read or write of has_clk
occurs first is undefined since there is no sequence point between them.

This is almost certainly just a typo/copy paste error and objectively
wrong, so just fix it.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2022-01-04 18:18:08 +01:00
Marcelina Kościelnicka
f84c9d8e17 memory_share: Fix SAT-based sharing for wide ports. 
Fixes #3117.
 2021-12-20 18:40:14 +01:00
Catherine
4f1d62d9b2 bugpoint: avoid infinite loop between -connections and -wires. 
Fixes #3113.
 2021-12-15 08:17:02 +00:00
Marcelina Kościelnicka
0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
 2021-12-12 19:56:50 +01:00
Marcelina Kościelnicka
1184a7f3b4 opt_mem_priority: Fix non-ascii char in help message. 
This is a fixed version of #3072.
 2021-12-09 00:56:14 +01:00
Lofty
77327b2544 sta: very crude static timing analysis pass 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2021-11-25 17:20:27 +01:00
Marcelina Kościelnicka
107aad2cd2 show: Fix wire bit indexing. 
Fixes #3078.
 2021-11-12 15:09:58 +01:00
Claire Xen
4699ddcc1b
Merge pull request #3077 from YosysHQ/claire/genlib 
Add genlib support to ABC command
 2021-11-10 20:02:34 +01:00