mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity

set initial state, only flip-flops

Browse source
This commit is contained in:
Miodrag Milanovic 2022-01-28 15:59:13 +01:00
parent cb12b7c4d8
commit ecbba625c4
1 changed files with 28 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

29
passes/sat/sim.cc
View file

@ -714,6 +714,28 @@ struct SimInstance
child.second->write_fst_step(f);
}
void setInitState(uint64_t time)
{
for (auto &it : ff_database)
{
Cell *cell = it.first;
SigSpec qsig = cell->getPort(ID::Q);
if (qsig.is_wire()) {
IdString name = qsig.as_wire()->name;
fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name));
if (id==0 && name.isPublic())
log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
if (id!=0) {
Const fst_val = Const::from_string(shared->fst->valueAt(id, time));
set_state(qsig, fst_val);
}
}
}
for (auto child : children)
child.second->setInitState(time);
}
bool checkSignals(uint64_t time)
{
bool retVal = false;
@ -730,8 +752,8 @@ struct SimInstance
retVal = true;
log("signal: %s fst: %s sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
}
//log("signal: %s fst: %s sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
}
//log("signal: %s fst: %s sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
}
for (auto child : children)
retVal |= child.second->checkSignals(time);
@ -992,11 +1014,16 @@ struct SimWorker : SimShared
}
auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
fst->reconstructAllAtTimes(edges);
bool initial = false;
for(auto &time : edges) {
for(auto &item : inputs) {
std::string v = fst->valueAt(item.second, time);
top->set_state(item.first, Const::from_string(v));
}
if (!initial) {
top->setInitState(time);
initial = true;
}
update();
bool status = top->checkSignals(time);