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https://github.com/YosysHQ/yosys
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Add support for various ff/latch cells simulation
This commit is contained in:
Miodrag Milanovic
parent
1586000048
commit
fb22d7cdc4
3 changed files with 260 additions and 171 deletions
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@ -22,6 +22,7 @@
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#include "kernel/celltypes.h"
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#include "kernel/mem.h"
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#include "kernel/fstdata.h"
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#include "kernel/ff.h"
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#include <ctime>
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@ -76,6 +77,7 @@ struct SimShared
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double stop_time = -1;
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SimulationMode sim_mode = SimulationMode::sim;
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bool cycles_set = false;
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const pool<IdString> ff_types = RTLIL::builtin_ff_cell_types();
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};
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void zinit(State &v)
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@ -113,8 +115,13 @@ struct SimInstance
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struct ff_state_t
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{
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State past_clock;
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Const past_d;
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Const past_ad;
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SigSpec past_clk;
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SigSpec past_ce;
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SigSpec past_srst;
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FfData data;
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};
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struct mem_state_t
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@ -209,10 +216,15 @@ struct SimInstance
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}
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}
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if (cell->type.in(ID($dff))) {
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if (shared->ff_types.count(cell->type)) {
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FfData ff_data(nullptr, cell);
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ff_state_t ff;
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ff.past_clock = State::Sx;
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ff.past_d = Const(State::Sx, cell->getParam(ID::WIDTH).as_int());
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ff.past_d = Const(State::Sx, ff_data.width);
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ff.past_ad = Const(State::Sx, ff_data.width);
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ff.past_clk = State::Sx;
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ff.past_ce = State::Sx;
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ff.past_srst = State::Sx;
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ff.data = ff_data;
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ff_database[cell] = ff;
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}
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@ -229,11 +241,10 @@ struct SimInstance
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{
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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zinit(ff.past_d);
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SigSpec qsig = cell->getPort(ID::Q);
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SigSpec qsig = it.second.data.sig_q;
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Const qdata = get_state(qsig);
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zinit(qdata);
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set_state(qsig, qdata);
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@ -466,20 +477,138 @@ struct SimInstance
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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FfData ff_data = ff.data;
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if (cell->type.in(ID($dff)))
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{
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bool clkpol = cell->getParam(ID::CLK_POLARITY).as_bool();
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State current_clock = get_state(cell->getPort(ID::CLK))[0];
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if (ff_data.has_clk) {
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// flip-flops
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State current_clk = get_state(ff_data.sig_clk)[0];
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if (clkpol ? (ff.past_clock == State::S1 || current_clock != State::S1) :
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(ff.past_clock == State::S0 || current_clock != State::S0))
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continue;
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// handle set/reset
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if (ff.data.has_sr) {
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Const current_q = get_state(ff.data.sig_q);
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Const current_clr = get_state(ff.data.sig_clr);
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Const current_set = get_state(ff.data.sig_set);
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if (set_state(cell->getPort(ID::Q), ff.past_d))
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did_something = true;
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for(int i=0;i<ff.past_d.size();i++) {
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if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
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current_q[i] = State::S0;
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}
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else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
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current_q[i] = State::S1;
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} else {
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// all below is in sync with clk
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if (ff_data.pol_clk ? (ff.past_clk == State::S1 || current_clk != State::S1) :
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(ff.past_clk == State::S0 || current_clk != State::S0))
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continue;
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if (ff_data.has_ce) {
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if (ff.past_ce == (ff_data.pol_ce ? State::S1 : State::S0))
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current_q[i] = ff.past_d[i];
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} else {
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current_q[i] = ff.past_d[i];
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}
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}
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}
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if (set_state(ff_data.sig_q, current_q))
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did_something = true;
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} else {
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// async reset
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if (ff_data.has_arst) {
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State current_arst = get_state(ff_data.sig_arst)[0];
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if (current_arst == (ff_data.pol_arst ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff_data.val_arst))
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did_something = true;
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continue;
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}
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}
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// async load
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if (ff_data.has_aload) {
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State current_aload = get_state(ff_data.sig_aload)[0];
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if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff.past_ad))
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did_something = true;
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continue;
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}
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}
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// all below is in sync with clk
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if (ff_data.pol_clk ? (ff.past_clk == State::S1 || current_clk != State::S1) :
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(ff.past_clk == State::S0 || current_clk != State::S0))
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continue;
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// chip enable priority over reset
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if (ff_data.ce_over_srst && ff_data.has_ce) {
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if (ff.past_ce != (ff_data.pol_ce ? State::S1 : State::S0))
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continue;
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}
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// handle sync reset
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if (ff_data.has_srst) {
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if (ff.past_srst == (ff_data.pol_srst ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff_data.val_srst))
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did_something = true;
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continue;
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}
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}
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// reset had priority over chip enable
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if (!ff_data.ce_over_srst && ff_data.has_ce) {
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if (ff.past_ce != (ff_data.pol_ce ? State::S1 : State::S0))
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continue;
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}
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if (set_state(ff_data.sig_q, ff.past_d))
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did_something = true;
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}
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} else {
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// handle set/reset
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if (ff.data.has_sr) {
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Const current_q = get_state(ff.data.sig_q);
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Const current_clr = get_state(ff.data.sig_clr);
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Const current_set = get_state(ff.data.sig_set);
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for(int i=0;i<current_q.size();i++) {
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if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
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current_q[i] = State::S0;
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}
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else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
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current_q[i] = State::S1;
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} else {
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if (ff_data.has_aload) {
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Const current_ad = get_state(ff.data.sig_ad);
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State current_aload = get_state(ff_data.sig_aload)[0];
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if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
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current_q[i] = current_ad[i];
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}
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}
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}
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}
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if (set_state(ff_data.sig_q, current_q))
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did_something = true;
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}
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// async load is true for all latches
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else if (ff_data.has_aload) {
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// async reset
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if (ff_data.has_arst) {
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State current_arst = get_state(ff_data.sig_arst)[0];
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if (current_arst == (ff_data.pol_arst ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff_data.val_arst))
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did_something = true;
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continue;
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}
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}
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State current_aload = get_state(ff_data.sig_aload)[0];
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if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, get_state(ff.data.sig_ad)))
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did_something = true;
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}
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} else if (ff_data.has_gclk) {
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// $ff
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if (set_state(ff_data.sig_q, ff.past_d))
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did_something = true;
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}
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}
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}
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@ -538,13 +667,22 @@ struct SimInstance
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{
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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if (cell->type.in(ID($dff))) {
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ff.past_clock = get_state(cell->getPort(ID::CLK))[0];
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ff.past_d = get_state(cell->getPort(ID::D));
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}
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if (ff.data.has_aload)
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ff.past_ad = get_state(ff.data.sig_ad);
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if (ff.data.has_clk || ff.data.has_gclk)
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ff.past_d = get_state(ff.data.sig_d);
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if (ff.data.has_clk)
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ff.past_clk = get_state(ff.data.sig_clk)[0];
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if (ff.data.has_ce)
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ff.past_ce = get_state(ff.data.sig_ce)[0];
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if (ff.data.has_srst)
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ff.past_srst = get_state(ff.data.sig_srst)[0];
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}
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for (auto &it : mem_database)
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@ -595,8 +733,7 @@ struct SimInstance
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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SigSpec sig_q = cell->getPort(ID::Q);
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SigSpec sig_q = it.second.data.sig_q;
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Const initval = get_state(sig_q);
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for (int i = 0; i < GetSize(sig_q); i++)
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@ -722,34 +859,32 @@ struct SimInstance
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child.second->write_fst_step(f);
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}
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void setInitState(uint64_t time)
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void setInitState()
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{
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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SigSpec qsig = cell->getPort(ID::Q);
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SigSpec qsig = it.second.data.sig_q;
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if (qsig.is_wire()) {
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IdString name = qsig.as_wire()->name;
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fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name));
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if (id==0 && name.isPublic())
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log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
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if (id!=0) {
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Const fst_val = Const::from_string(shared->fst->valueAt(id, time));
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Const fst_val = Const::from_string(shared->fst->valueOf(id));
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set_state(qsig, fst_val);
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}
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}
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}
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for (auto child : children)
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child.second->setInitState(time);
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child.second->setInitState();
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}
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bool checkSignals(uint64_t time)
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bool checkSignals()
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{
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bool retVal = false;
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for(auto &item : fst_handles) {
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if (item.second==0) continue; // Ignore signals not found
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Const fst_val = Const::from_string(shared->fst->valueAt(item.second, time));
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Const fst_val = Const::from_string(shared->fst->valueOf(item.second));
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Const sim_val = get_state(item.first);
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if (sim_val.size()!=fst_val.size())
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log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
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@ -779,7 +914,7 @@ struct SimInstance
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}
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}
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for (auto child : children)
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retVal |= child.second->checkSignals(time);
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retVal |= child.second->checkSignals();
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return retVal;
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}
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};
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@ -998,8 +1133,6 @@ struct SimWorker : SimShared
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log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
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fst_clock.push_back(id);
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}
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if (fst_clock.size()==0)
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log_error("No clock signals defined for input file\n");
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SigMap sigmap(topmod);
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std::map<Wire*,fstHandle> inputs;
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@ -1044,37 +1177,48 @@ struct SimWorker : SimShared
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if (stopCount<startCount) {
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log_error("Stop time is before start time\n");
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}
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auto samples = fst->getAllEdges(fst_clock, startCount, stopCount);
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// Limit to number of cycles if provided
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if (cycles_set && ((size_t)(numcycles *2) < samples.size()))
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samples.erase(samples.begin() + (numcycles*2), samples.end());
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// Add setup time (start time)
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if (samples.empty() || samples.front()!=startCount)
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samples.insert(samples.begin(), startCount);
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fst->reconstructAllAtTimes(samples);
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bool initial = true;
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int cycle = 0;
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log("Co-simulation from %lu%s to %lu%s\n", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
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for(auto &time : samples) {
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log("Co-simulating cycle %d [%lu%s].\n", cycle, (unsigned long)time, fst->getTimescaleString());
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for(auto &item : inputs) {
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std::string v = fst->valueAt(item.second, time);
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top->set_state(item.first, Const::from_string(v));
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}
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if (initial) {
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top->setInitState(time);
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initial = false;
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}
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update();
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log("Co-simulation from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
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if (cycles_set)
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log(" for %d clock cycle(s)",numcycles);
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log("\n");
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bool all_samples = fst_clock.empty();
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bool status = top->checkSignals(time);
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if (status)
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log_error("Signal difference\n");
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cycle++;
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try {
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fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
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log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
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for(auto &item : inputs) {
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std::string v = fst->valueOf(item.second);
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top->set_state(item.first, Const::from_string(v));
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}
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if (initial) {
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top->setInitState();
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write_output_header();
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initial = false;
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}
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update();
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write_output_step(5*cycle);
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bool status = top->checkSignals();
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if (status)
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log_error("Signal difference\n");
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cycle++;
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// Limit to number of cycles if provided
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if (cycles_set && cycle > numcycles *2)
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throw fst_end_of_data_exception();
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if (time==stopCount)
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throw fst_end_of_data_exception();
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});
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} catch(fst_end_of_data_exception) {
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// end of data detected
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}
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write_output_step(5*(cycle-1)+2);
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write_output_end();
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if (writeback) {
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pool<Module*> wbmods;
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top->writeback(wbmods);
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