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yosys/passes
History
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
..
cmds Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
hierarchy verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
memory memory_bram: Make use of new mem emulation functions to map more RAMs. 2022-01-27 19:31:27 +01:00
opt opt_dff: Don't mutate muxes while ModWalker is active. 2022-01-28 08:55:56 +01:00
pmgen Make it work on all 2021-11-05 10:51:58 +01:00
proc proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
sat Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
techmap Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00