mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Display values of outputs

Browse source
This commit is contained in:
Miodrag Milanovic 2022-01-26 16:52:36 +01:00
parent 226dc659f0
commit 40018e191b
1 changed files with 10 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

22
passes/sat/sim.cc
View file

@ -885,6 +885,7 @@ struct SimWorker : SimShared
SigMap sigmap(topmod);
log ("Get inputs\n");
std::map<Wire*,fstHandle> inputs;
std::map<Wire*,fstHandle> outputs;
for (auto wire : topmod->wires()) {
if (wire->port_input) {
@ -892,6 +893,11 @@ struct SimWorker : SimShared
log("Input %s\n",log_id(wire));
inputs[wire] = id;
}
if (wire->port_output) {
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
log("Output %s %d\n",log_id(wire), id);
outputs[wire] = id;
}
}
fst->reconstruct(fst_clock);
@ -903,19 +909,11 @@ struct SimWorker : SimShared
top->set_state(item.first, Const::from_string(v));
}
update();
/*Wire *wire = topmod->wire("\\cnt");
Const value = top->get_state(wire);
std::stringstream ss;
for (int i = GetSize(value)-1; i >= 0; i--) {
switch (value[i]) {
case State::S0: ss << "0"; break;
case State::S1: ss << "1"; break;
case State::Sx: ss << "x"; break;
default: ss << "z";
}
for(auto &item : outputs) {
Const fst_val = Const::from_string(fst->valueAt(item.second, time));
Const sim_val = top->get_state(item.first);
log("%s %s\n", log_signal(fst_val), log_signal(sim_val));
}
log("%s\n",ss.str().c_str());*/
}
}
};