Emil J. Tywoniak
a287c24e75
design: properly switch signorm mode when restoring saved designs
2026-04-09 13:16:37 +02:00
Emil J. Tywoniak
98c7078984
equiv_make: don't copy $input_port
2026-04-08 11:40:19 +02:00
Emil J. Tywoniak
c7e56da381
Revert "techmap: call hierarchy on map files to determine port directions"
...
This reverts commit eabbf6d225
2026-04-02 11:40:33 +02:00
Emil J. Tywoniak
8bc1aac882
hierarchy: tolerance for apparent recursive instances in techmap files
2026-04-01 13:12:41 +02:00
Emil J. Tywoniak
eabbf6d225
techmap: call hierarchy on map files to determine port directions
2026-04-01 12:46:31 +02:00
Emil J. Tywoniak
9f5a95469d
memory: add -bram-register
2026-03-31 14:59:59 +02:00
Emil J. Tywoniak
0f3efd2c1a
fixup! memory_bram: add -register
2026-03-31 14:59:34 +02:00
Emil J. Tywoniak
4fcd50ed7a
memory_bram: add -register
2026-03-31 14:59:10 +02:00
Robert O'Callahan
087ebdd6e4
Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.
2026-03-27 15:16:08 +01:00
Emil J. Tywoniak
b1457934ab
sort: init
2026-03-27 15:13:47 +01:00
Emil J. Tywoniak
d33d048874
fixup! opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
2026-03-25 12:39:33 +01:00
Emil J. Tywoniak
1775bce173
opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
2026-03-25 11:50:17 +01:00
Emil J. Tywoniak
c416d39ebb
techmap: read_verilog -icells, I mean, obviously
2026-03-24 23:25:42 +01:00
Emil J. Tywoniak
09040adb2c
connect: remove input ports on conflict
2026-03-24 23:23:27 +01:00
Emil J. Tywoniak
15665773fd
opt_dff: sigma harder, FfDataSigMapped
2026-03-24 23:22:39 +01:00
Emil J. Tywoniak
734249a5e6
opt_dff: temporarily disable signorm due to muxtree traversal
2026-03-24 23:22:39 +01:00
Emil J. Tywoniak
872c940259
design: fix signorm commit connectivity to design
2026-03-18 00:44:20 +01:00
Emil J. Tywoniak
55189bc65c
flatten: redo signormalization to work around fanout issue
2026-03-17 18:04:41 +01:00
Emil J. Tywoniak
c01d88c303
signorm: disable passes that use rewrite_sigspecs
2026-03-17 17:35:57 +01:00
Emil J. Tywoniak
c5d4b435bd
check: stitch info about $connect ports together for driver analysis
2026-03-17 17:29:23 +01:00
Emil J. Tywoniak
3257b8ae1e
abstract: skip $input_port cells
2026-03-17 16:34:41 +01:00
Emil J. Tywoniak
9d3928c014
flatten: skip $input_port cells in template module
2026-03-17 16:11:32 +01:00
Emil J. Tywoniak
869a7303b0
signorm: disable in passes that use swap_names
2026-03-16 22:45:29 +01:00
Emil J. Tywoniak
3502a51598
opt_expr: fix invert_map
2026-03-13 12:18:48 +01:00
Emil J. Tywoniak
e7a97360a8
techmap: disable signorm more
2026-03-12 22:11:06 +01:00
Emil J. Tywoniak
04311e3e53
techmap: disable signorm
2026-03-11 21:30:27 +01:00
Emil J. Tywoniak
8bad1a2035
opt_hier: disable signorm
2026-03-11 21:26:12 +01:00
Emil J. Tywoniak
d39ce10601
opt_merge_inc: re add initvals deletion
2026-03-11 12:35:16 +01:00
Emil J. Tywoniak
8375f11fa5
wreduce: fixup initvals after setPort
2026-03-10 14:01:57 +01:00
Emil J. Tywoniak
7c5128a08a
check: don't fail on $input_port
2026-03-07 00:42:01 +01:00
Jannis Harder
eae87b3161
WIP half broken snapshot
2025-10-06 14:39:25 +02:00
Emil J
7719beb4ae
Merge pull request #5349 from rocallahan/cleanup-hashops
...
Reduce hashops verbiage in `OptMergePass`
2025-09-30 19:34:44 +02:00
Jannis Harder
47639f8a98
Merge pull request #5388 from jix/bufnorm-followup
...
Refactor and fixes to incremental bufNormalize + related changes
2025-09-29 15:15:29 +02:00
Jannis Harder
6a7372626a
Merge pull request #5389 from jix/sva_continue
...
verific: New `-sva-continue-on-error` import option
2025-09-29 15:07:54 +02:00
Emil J
87c1a868d3
Merge pull request #5384 from rocallahan/simplify-opt-merge-logic
...
Move `OptMerge` cell filtering logic to happen while building the cell vector
2025-09-29 15:03:01 +02:00
Martin Povišer
a9318db2fa
opt_hier: Adjust messages
2025-09-29 12:27:27 +02:00
Martin Povišer
ffe2f7a16d
opt_hier: Fix two optimizations conflicting
...
Fix a conflict between the following two:
* propagation of tied-together inputs in
* propagation of unused inputs out
2025-09-29 12:27:27 +02:00
Jannis Harder
cbc1055517
opt_clean: Fix debug output when cleaning up bufnorm cells
2025-09-29 08:21:28 +02:00
Jannis Harder
9396e5e5fe
portarcs: Ignore all bufnorm helper cells
...
The `portarcs` pass was already ignoring `$buf` cells when loading
timing data, but now bufnorm will also emit `$input_port` and `$connect`
helper cells, which need to be ignored as well.
2025-09-29 08:21:28 +02:00
Jannis Harder
ce5d04a42f
hierarchy: Suggest more specific command to skip unsupported SVA
2025-09-26 18:41:26 +02:00
KrystalDelusion
7ebd972165
Merge pull request #5277 from YosysHQ/krys/fix_4983_alt
...
autoname: Avoid integer overflow
2025-09-26 14:11:20 +12:00
Krystine Sherwin
fef6bdae6c
autoname.cc: Return number of renames
...
Was previously the number of proposed renames, but since renames can be skipped this causes the final count to differ from the number of actually renamed objects.
Check counts in `tests/various/autoname.ys`.
2025-09-26 11:05:50 +12:00
Emil J
8c8d18f2d8
Merge pull request #5392 from rocallahan/opt-merge-cleanup
...
Some small readability improvements to `OptMergeWorker`
2025-09-25 12:15:33 +02:00
Martin Povišer
29e0144ebc
Merge pull request #5381 from povik/abc9-multilib
...
Support multiple lib files in abc9_exe
2025-09-25 09:45:09 +02:00
Robert O'Callahan
4d209c187d
Switch OptMergeWorker cell type switching to use IdString::in()
2025-09-25 03:06:58 +00:00
Robert O'Callahan
1c73011e7e
Swap SigSpecs using std::swap with moves
2025-09-25 03:04:17 +00:00
Jannis Harder
83dd99efb7
verific: New -sva-continue-on-error import option
...
This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
2025-09-24 18:58:54 +02:00
Jannis Harder
71882debe7
simplemap: Remove leftover debug output
2025-09-24 13:20:27 +02:00
Jannis Harder
904d49c6d8
abc9_ops: Remove temporary debug log message
...
I missed this when adding the -replace_zbufs option.
2025-09-24 13:20:27 +02:00
Jannis Harder
7a69dbb63d
Merge pull request #5372 from rocallahan/abc-done
...
Make ABC_DONE tracking more robust
2025-09-24 08:40:26 +02:00
