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opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
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@ -1213,7 +1213,7 @@ skip_fine_alu:
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}
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}
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if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
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if (!keepdc && cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
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{
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RTLIL::SigSpec a = cell->getPort(ID::A);
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RTLIL::SigSpec b = cell->getPort(ID::B);
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