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2026-04-15 08:44:11 +00:00
Code
Activity
a287c24e75
yosys
/
passes
History
Emil J. Tywoniak
a287c24e75
design: properly switch signorm mode when restoring saved designs
2026-04-09 13:16:37 +02:00
..
cmds
design: properly switch signorm mode when restoring saved designs
2026-04-09 13:16:37 +02:00
equiv
equiv_make: don't copy $input_port
2026-04-08 11:40:19 +02:00
fsm
Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()
2025-09-16 23:02:16 +00:00
hierarchy
hierarchy: tolerance for apparent recursive instances in techmap files
2026-04-01 13:12:41 +02:00
memory
memory: add -bram-register
2026-03-31 14:59:59 +02:00
opt
Move
Design::sort()
calls out of
opt
and
opt_clean
passes into the synth passes that need them.
2026-03-27 15:16:08 +01:00
pmgen
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
proc
Update passes/proc to avoid bits()
2025-09-16 03:17:23 +00:00
sat
signorm: disable passes that use rewrite_sigspecs
2026-03-17 17:35:57 +01:00
techmap
Revert "techmap: call hierarchy on map files to determine port directions"
2026-04-02 11:40:33 +02:00
tests
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00