Dhaval
a14ca53449
Merge eb5a9cc96a into 5fd39ff3e1
2026-03-20 20:16:12 +13:00
Robert O'Callahan
13d9fffdb9
Work around std::reverse miscompilation with empty range
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This causes problems when compiling with fuzzing instrumenation enabled.
2026-03-06 02:03:21 +00:00
Emil J
629bf3dffd
Merge pull request #5630 from apullin/array-assignment
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ast: Add support for array-to-array assignment
2026-03-05 11:10:12 +00:00
Andrew Pullin
6ac8c8cb05
ast: Add support for array-to-array assignment
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This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:
1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`
Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.
Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
2026-03-04 21:34:40 -08:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes
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celltypes: compile-time lookup tables for internal cells
2026-03-04 14:47:57 +00:00
Emil J. Tywoniak
ecb8b20f62
yosys: use newcelltypes for yosys_celltypes users
2026-03-04 12:39:44 +01:00
likeamahoney
e9442194f2
support automatic lifetime qualifier on procedural variables
2026-02-27 20:42:52 +03:00
Miodrag Milanovic
eb5a9cc96a
More templates
2026-02-23 13:04:55 +01:00
Miodrag Milanovic
d52cad1ae2
Remove not needed initialization
2026-02-23 12:40:48 +01:00
Miodrag Milanovic
c5023dce7a
Use templates where applicable
2026-02-23 12:06:06 +01:00
Emil J
13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks
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aigerparse: add some bounds checks
2026-02-20 11:53:49 +01:00
Dhaval Chaudhari
6435b4a643
Add applied vlog extensions management and apply_all method
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Enhance YosysVerificSettings by introducing a vector to track applied SystemVerilog file extensions, ensuring stale mappings are removed before adding new extensions. Implement an apply_all method to apply all settings to Verific APIs after a reset, improving settings management and consistency.
2026-02-20 10:26:41 +05:30
Emil J
33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check
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blifparse: add bounds check
2026-02-18 12:18:05 +01:00
Gus Smith
12ace45b89
Support param. default values in JSON FE and SV BE
2026-02-11 08:10:55 -08:00
Lofty
2e03ee1434
aigerparse: sanity-check AIGER header
2026-02-11 11:46:17 +00:00
Emil J. Tywoniak
43a15113ff
aigerparse: add some bounds checks
2026-02-11 12:35:16 +01:00
Emil J. Tywoniak
3f1fbfdaee
blifparse: add bounds check
2026-02-11 12:16:02 +01:00
Sean Luchen
224549fb88
Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
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Signed-off-by: Sean Luchen <seanluchen@google.com>
2026-02-02 15:26:03 -08:00
Miodrag Milanovic
b70f527c67
verific: fixed -sv2017 option and added ability to set VHDL standard if applicable
2026-01-29 10:32:30 +01:00
Miodrag Milanović
43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl
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Upstream verific mixed sv vhdl
2026-01-29 10:12:09 +01:00
Natalia
8d504ecb48
verific: use MFCU for SV file list
2026-01-29 00:03:28 -08:00
Natalia
188082551a
verific: only use MFCU when VHDL present
2026-01-28 03:37:08 -08:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived
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Avoid `module_not_derived` on internal cells in techmap result
2026-01-26 14:48:40 -08:00
Emil J
5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main
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Add gatesi_mode to init gates under gates_mode in BLIF format
2026-01-26 23:30:11 +01:00
nataliakokoromyti
f3c87610f5
verific: allow mixed SV/VHDL in -f files
2026-01-24 23:46:45 -08:00
Dhaval Chaudhari
75501ada55
remove option
2026-01-20 19:26:12 +05:30
Dhaval Chaudhari
bd710134fc
Refactor Yosys-Verific settings structure
2026-01-20 18:14:02 +05:30
Dhaval Chaudhari
276136cd50
Add Yosys-Verific settings management
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Introduce a new structure for managing Yosys-Verific settings, allowing users to get, set, and reset options related to Verific integration. Implement options for ignoring translate pragmas and specifying file extensions for SystemVerilog. Update command-line interface to support these settings, including help documentation for usage examples.
2026-01-20 16:05:27 +05:30
Miodrag Milanovic
d0fa4781c6
verific: Fix -sv2017 message and formatting
2026-01-20 08:07:26 +01:00
Martin Povišer
f67d4bcfa4
verilog: Do not set module_not_derived on internal cells
2026-01-19 16:48:13 -08:00
Miodrag Milanovic
cc3038f468
verific: Fix -sv2017 message
2026-01-19 16:32:46 +01:00
Miodrag Milanovic
d095d2c405
verific: add explicit System Verilog 2017 option
2026-01-16 07:56:53 +01:00
kamay
e0077b188d
Add gatesi_mode in BLIF format
2026-01-14 21:41:56 +01:00
Emil J
71feb2a2a1
Merge pull request #5604 from YosysHQ/emil/read_verilog-remove-log
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read_verilog: remove log I left behind by accident
2026-01-13 17:48:30 +00:00
Emil J. Tywoniak
83c1364eeb
read_verilog: remove log I left behind by accident
2026-01-13 18:47:23 +01:00
Emil J
5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire
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Add autowires in genblk/for expension
2026-01-13 16:40:22 +01:00
Emil J
0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz
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Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
2026-01-06 20:07:31 +01:00
N. Engelhardt
d5b38af4a7
Merge pull request #5550 from YosysHQ/nak/dont_merge_properties
2025-12-22 16:54:43 +01:00
Robert O'Callahan
46cb05c471
Pass IdString by value instead of by const reference.
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When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
2025-12-22 01:52:59 +00:00
Robert O'Callahan
ddd6a16ee0
Add -legalize option to read_rtlil
2025-12-21 21:47:48 +00:00
N. Engelhardt
45d654e2d7
avoid merging formal properties
2025-12-17 20:25:24 +01:00
Yannick Lamarre
9814f9dc4f
Add autowires in genblk/for expension
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Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>
2025-12-10 14:43:42 +01:00
Emil J
9871e9b17e
Merge pull request #5496 from YosysHQ/emil/liberty-flop-loops
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read_liberty: support loopy retention cells
2025-12-01 22:50:20 +01:00
Robert O'Callahan
8f0ecce53f
Forbid creating IdStrings and incrementing autoidx during multithreaded phases, and add dynamic checks for that
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We could make it safe to increment autoidx during multithreaded passes, but that's
actually undesirable because it would lead to nondeterminism. If/when we need new
IDs during parallel passes, we'll have to figure out how to allocate them in a
deterministic way, and that will depend on the details of what the pass does.
So don't try to tackle that now.
2025-11-25 21:57:46 +00:00
Mike Inouye
f098352ae6
Enable xaiger2 pass when not in NDEBUG
2025-11-21 14:23:32 -08:00
Emil J. Tywoniak
d5c1cd8fc0
read_liberty: support loopy retention cells
2025-11-20 13:21:32 +01:00
Emil J. Tywoniak
302643330c
read_liberty: add cell context to more errors, remove log_id
2025-11-20 13:21:28 +01:00
KrystalDelusion
529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params
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Handle unsized params
2025-11-12 07:14:44 +13:00
Emil J. Tywoniak
8f53d21ea7
simplify: refactor specific package import
2025-11-10 14:26:10 +01:00
Rahul Bhagwat
54e5eb1c3c
no use vector
2025-11-08 23:16:52 +05:30
