Dhaval Chaudhari 276136cd50 Add Yosys-Verific settings management ... Introduce a new structure for managing Yosys-Verific settings, allowing users to get, set, and reset options related to Verific integration. Implement options for ignoring translate pragmas and specifying file extensions for SystemVerilog. Update command-line interface to support these settings, including help documentation for usage examples.		2026-01-20 16:05:27 +05:30
..
aiger	Remove .c_str() from parameters to log_debug()	2025-09-23 19:10:33 +12:00
aiger2	Enable xaiger2 pass when not in NDEBUG	2025-11-21 14:23:32 -08:00
ast	Merge pull request #4235 from ylm/genblk_wire	2026-01-13 16:40:22 +01:00
blif	Forbid creating IdStrings and incrementing autoidx during multithreaded phases, and add dynamic checks for that	2025-11-25 21:57:46 +00:00
json	Use fast path for 32-bit Const integer constructor in more places	2025-09-16 03:17:24 +00:00
liberty	read_liberty: support loopy retention cells	2025-11-20 13:21:32 +01:00
rpc	Remove .c_str() from parameters to log_debug()	2025-09-23 19:10:33 +12:00
rtlil	Add -legalize option to read_rtlil	2025-12-21 21:47:48 +00:00
verific	Add Yosys-Verific settings management	2026-01-20 16:05:27 +05:30
verilog	read_verilog: remove log I left behind by accident	2026-01-13 18:47:23 +01:00