3827 commits

Author	SHA1	Message	Date
Eddie Hung	b3a66dff7c	Move \init signal for non-port signals as long as internally driven	2019-11-28 12:57:36 -08:00
Eddie Hung	130d3b9639	Fix multiple driver issue	2019-11-27 13:23:31 -08:00
Eddie Hung	ac5b5e97bc	Fix multiple driver issue	2019-11-27 13:21:59 -08:00
Eddie Hung	4bac6b13be	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-27 10:17:10 -08:00
Eddie Hung	cd2af66099	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-27 08:19:13 -08:00
Eddie Hung	1c0ee4f786	Do not replace constants with same wire	2019-11-27 08:18:41 -08:00
Eddie Hung	6464dc35ec	Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd ... xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder	2019-11-27 08:00:22 -08:00
Clifford Wolf	41e0ddf4f4	Merge pull request #1501 from YosysHQ/dave/mem_copy_attr ... memory_collect: Copy attr from RTLIL::Memory to cell	2019-11-27 11:25:23 +01:00
Eddie Hung	6338615aa1	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-27 01:02:16 -08:00
Eddie Hung	c7aa2c6b79	Cleanup	2019-11-27 01:01:24 -08:00
Eddie Hung	cb05fe0f70	Check for nullptr	2019-11-27 00:51:39 -08:00
Eddie Hung	d960feeeb0	Stray log_dump	2019-11-27 00:50:25 -08:00
Eddie Hung	8c813632b6	Revert "submod to bitty rather bussy, for bussy wires used as input and output" ... This reverts commit cba3073026.	2019-11-27 00:48:22 -08:00
Eddie Hung	969f511415	Promote output wires in sigmap so that can be detected	2019-11-26 23:39:14 -08:00
Eddie Hung	5e487b103c	Fix submod -hidden	2019-11-26 23:26:25 -08:00
Eddie Hung	435d33c373	Add -hidden option to submod	2019-11-26 23:26:12 -08:00
Marcin Kościelnicki	fdcbda195b	opt_share: Fix handling of fine cells. ... Fixes #1525.	2019-11-27 08:01:07 +01:00
Eddie Hung	2105ae176a	Check for either sign or zero extension for postAdd packing	2019-11-26 22:51:00 -08:00
Eddie Hung	09637dd3e4	Fix submod -hidden	2019-11-26 11:57:26 -08:00
Eddie Hung	3027f015c2	clkpart to use 'submod -hidden'	2019-11-26 11:35:32 -08:00
Eddie Hung	e8aa92ca35	Add -hidden option to submod	2019-11-26 11:35:15 -08:00
Eddie Hung	eb666b4677	Update docs with bullet points	2019-11-26 11:12:58 -08:00
Eddie Hung	0d7ba77426	Move \init from source wire to submod if output port	2019-11-25 16:07:47 -08:00
Eddie Hung	6831510f5b	Fix debug	2019-11-25 12:59:34 -08:00
Eddie Hung	d087024caf	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-25 12:42:09 -08:00
Eddie Hung	180cb39395	abc9 to contain time call	2019-11-25 12:35:57 -08:00
Eddie Hung	f50b6422b0	abc9 to no longer to clock partitioning, operate on whole modules only	2019-11-25 12:35:38 -08:00
Eddie Hung	63b7a48fbc	clkpart to analyse async flops too	2019-11-25 12:04:11 -08:00
Marcin Kościelnicki	6cdea425b8	clkbufmap: Add support for inverters in clock path.	2019-11-25 20:40:39 +01:00
Eddie Hung	23ecf12bbf	Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff	2019-11-23 10:29:03 -08:00
Eddie Hung	15aa3f460d	More oopsies	2019-11-23 10:28:46 -08:00
Eddie Hung	bf1167bc64	Conditioning abc9 on POs not accurate due to cells	2019-11-23 10:26:55 -08:00
Eddie Hung	7b2bccb3d3	Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff	2019-11-23 10:18:06 -08:00
Eddie Hung	722eeacc09	Print ".en=" only if there is an enable signal	2019-11-23 10:17:31 -08:00
Eddie Hung	907c8aeaef	Escape IdStrings	2019-11-23 10:16:56 -08:00
Eddie Hung	165f5cb6cf	More sane naming of submod	2019-11-23 10:01:09 -08:00
Eddie Hung	66ff0511a0	Add -set_attr option, -unpart to take attr name	2019-11-23 09:52:17 -08:00
Eddie Hung	fb49da21bd	Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff	2019-11-23 08:39:19 -08:00
Eddie Hung	96941aacbb	Do not use log_signal() for empty SigSpec to prevent "{ }"	2019-11-22 23:29:10 -08:00
Eddie Hung	736b96b186	Call submod once, more meaningful submod names, ignore largest domain	2019-11-22 23:16:15 -08:00
Eddie Hung	1851f4b488	Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff	2019-11-22 23:01:18 -08:00
Eddie Hung	d223e11a72	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 22:28:35 -08:00
Eddie Hung	cba3073026	submod to bitty rather bussy, for bussy wires used as input and output	2019-11-22 20:53:58 -08:00
Eddie Hung	900c806d4e	Move clkpart into passes/hierarchy	2019-11-22 17:25:53 -08:00
Eddie Hung	2c5dfd802d	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 17:24:45 -08:00
Eddie Hung	8119383f81	Constant driven signals are also an input to submodules	2019-11-22 17:23:51 -08:00
Eddie Hung	89a4a4d90f	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 17:04:33 -08:00
Eddie Hung	573396851a	Oops	2019-11-22 17:03:30 -08:00
Eddie Hung	bf7d36627e	Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff	2019-11-22 17:00:35 -08:00
Eddie Hung	95af8f56e4	Only action if there is more than one clock domain	2019-11-22 17:00:11 -08:00