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	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
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						commit
						cd2af66099
					
				
					 1 changed files with 3 additions and 7 deletions
				
			
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			@ -34,7 +34,6 @@ struct SubmodWorker
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	RTLIL::Design *design;
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	RTLIL::Module *module;
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	SigMap sigmap;
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	std::map<RTLIL::SigBit, RTLIL::SigBit> replace_const;
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	bool copy_mode;
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	bool hidden_mode;
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			@ -231,7 +230,9 @@ struct SubmodWorker
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				if (new_wire->port_id > 0) {
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					// Prevents "ERROR: Mismatch in directionality ..." when flattening
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					if (new_wire->port_output)
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						old_sig.replace(replace_const);
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						for (auto &b : old_sig)
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							if (!b.wire)
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								b = module->addWire(NEW_ID);
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					new_cell->setPort(new_wire->name, old_sig);
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				}
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			}
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			@ -265,11 +266,6 @@ struct SubmodWorker
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			if (wire->port_output)
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				sigmap.add(wire);
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		}
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		auto wire = module->addWire(NEW_ID);
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		replace_const.emplace(State::S0, wire);
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		replace_const.emplace(State::S1, wire);
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		replace_const.emplace(State::Sx, wire);
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		replace_const.emplace(State::Sz, wire);
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		if (opt_name.empty())
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		{
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