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https://github.com/YosysHQ/yosys
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parent
0466c48533
commit
fdcbda195b
2 changed files with 24 additions and 4 deletions
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@ -83,7 +83,9 @@ struct ExtSigSpec {
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bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; }
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};
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#define BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($and), ID($or), ID($xor), ID($xnor)
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#define FINE_BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)
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#define BITWISE_OPS FINE_BITWISE_OPS, ID($and), ID($or), ID($xor), ID($xnor)
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#define REDUCTION_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($reduce_nand)
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@ -250,14 +252,19 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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shared_op->setPort(ID(CO), alu_co.extract(0, conn_width));
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}
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shared_op->setParam(ID(Y_WIDTH), conn_width);
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bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
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if (!is_fine)
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shared_op->setParam(ID(Y_WIDTH), conn_width);
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if (decode_port(shared_op, ID::A, &assign_map) == operand) {
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shared_op->setPort(ID::B, mux_to_oper);
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shared_op->setParam(ID(B_WIDTH), max_width);
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if (!is_fine)
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shared_op->setParam(ID(B_WIDTH), max_width);
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} else {
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shared_op->setPort(ID::A, mux_to_oper);
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shared_op->setParam(ID(A_WIDTH), max_width);
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if (!is_fine)
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shared_op->setParam(ID(A_WIDTH), max_width);
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}
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}
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