879 commits

Author	SHA1	Message	Date
Eddie Hung	99267f660f	Fix spacing	2019-06-12 09:21:52 -07:00
Eddie Hung	738fdfe8f5	Remove wide mux inference	2019-06-12 09:20:46 -07:00
Eddie Hung	1e838a8913	Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"	2019-06-12 08:49:15 -07:00
Eddie Hung	4c9fde87d1	Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" ... This reverts commit 2dffa4685b.	2019-06-12 08:48:45 -07:00
Eddie Hung	2dffa4685b	Add "-W' wire delay arg to abc9, use from synth_xilinx	2019-06-11 17:10:47 -07:00
Eddie Hung	54379f9872	Disable dist RAM boxes due to comb loop	2019-06-11 12:02:51 -07:00
Eddie Hung	8a708d1fdb	Remove #ifndef ABC	2019-06-11 12:02:31 -07:00
Eddie Hung	b77c5da769	Revert "Revert "Move ff_map back after ABC for shregmap"" ... This reverts commit e473e74565.	2019-06-10 14:37:09 -07:00
Eddie Hung	a1d4ae78a0	Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" ... This reverts commit 94a5f4e609.	2019-06-10 14:34:43 -07:00
Eddie Hung	352c532bb2	Merge remote-tracking branch 'origin/master' into xc7mux	2019-06-10 11:02:54 -07:00
Simon Schubert	abf90b0403	ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k	2019-06-10 11:49:08 +02:00
Eddie Hung	816b5f5891	Comment out muxpack (currently broken)	2019-06-07 16:58:57 -07:00
Eddie Hung	88ae13e6a5	$__XILINX_MUX_ -> $__XILINX_SHIFTX	2019-06-06 15:32:36 -07:00
Eddie Hung	d3b7ae218b	Fix muxcover and its techmapping	2019-06-06 15:31:18 -07:00
Eddie Hung	a8c49168fb	Run muxpack and muxcover in synth_xilinx	2019-06-06 14:43:08 -07:00
Eddie Hung	7166dbe418	Remove abc_flop attributes for now	2019-06-06 14:35:38 -07:00
Eddie Hung	eaee250a6e	Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux	2019-06-06 14:06:59 -07:00
David Shah	30cedaca10	Merge pull request #1073 from whitequark/ecp5-diamond-iob ... ECP5: implement most Diamond I/O buffer primitives	2019-06-06 11:22:49 +01:00
whitequark	f3a26730b6	ECP5: implement all Diamond I/O buffer primitives.	2019-06-06 10:18:33 +00:00
Eddie Hung	6ed15b7890	Update abc attributes on FD*E_1	2019-06-05 12:33:40 -07:00
Eddie Hung	67f744d428	Cleanup	2019-06-05 12:28:46 -07:00
Eddie Hung	2c18d530ea	Call shregmap -tech xilinx_static	2019-06-05 12:28:26 -07:00
Eddie Hung	e473e74565	Revert "Move ff_map back after ABC for shregmap" ... This reverts commit 9b9bd4e19f.	2019-06-05 11:53:06 -07:00
Eddie Hung	94a5f4e609	Rename shregmap -tech xilinx -> xilinx_dynamic	2019-06-04 14:34:36 -07:00
Eddie Hung	82d41bc2f2	Add space between -D and _ABC	2019-06-04 11:54:08 -07:00
Eddie Hung	f0e93f33cf	Add (* abc_flop_q *) to brams_bb.v	2019-06-04 11:53:51 -07:00
Eddie Hung	6cf092641f	Fix name clash	2019-06-04 09:56:36 -07:00
Eddie Hung	e260150321	Add mux_map.v for wide mux	2019-06-04 09:51:47 -07:00
Eddie Hung	9b9bd4e19f	Move ff_map back after ABC for shregmap	2019-06-03 23:43:23 -07:00
Eddie Hung	09b778744d	Respect -nocarry	2019-06-03 23:42:30 -07:00
Eddie Hung	5afa42432f	Fix pmux2shiftx logic	2019-06-03 23:29:45 -07:00
Eddie Hung	23a73ca624	Merge mistake	2019-06-03 23:19:22 -07:00
Eddie Hung	f81a0ed92e	Merge remote-tracking branch 'origin/master' into xc7mux	2019-06-03 23:07:08 -07:00
Eddie Hung	b6e59741ae	Typo	2019-06-03 20:21:41 -07:00
Eddie Hung	02973474df	Remove extra newline	2019-06-03 20:04:47 -07:00
Eddie Hung	c9a0bac541	IS_C_INVERTED	2019-06-03 19:45:56 -07:00
Eddie Hung	0ad50332d9	Execute techmap and arith_map simultaneously	2019-06-03 19:36:09 -07:00
Eddie Hung	ebcc85b9b8	Fix `ifndef	2019-06-03 12:37:02 -07:00
Eddie Hung	0092770317	Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)	2019-06-03 12:34:55 -07:00
Eddie Hung	4da25c76b3	Ooopsie	2019-06-03 09:33:42 -07:00
Eddie Hung	9f44a71715	Consistent with xilinx	2019-06-03 09:23:43 -07:00
Eddie Hung	2228cef62f	Add flops as blackboxes	2019-05-31 18:11:46 -07:00
Eddie Hung	01f71085f2	Add FD*E_1 -> FD*E techmap rules	2019-05-31 18:11:24 -07:00
Eddie Hung	dea36d4366	Techmap flops before ABC again	2019-05-31 18:10:25 -07:00
Eddie Hung	eb08e71bd1	Merge branch 'xaig' into xc7mux	2019-05-31 13:03:03 -07:00
Eddie Hung	1ad33c3b5a	Remove whitebox attribute from DRAMs for now	2019-05-30 13:07:29 -07:00
Eddie Hung	fdfc18be91	Carry in/out to be the last input/output for chains to be preserved	2019-05-30 01:23:36 -07:00
Eddie Hung	276f5f8b81	Some more realistic delays...	2019-05-29 22:55:34 -07:00
Eddie Hung	f228621b80	Typo	2019-05-28 09:36:01 -07:00
Eddie Hung	e032e5bcde	Make MUXF{7,8} and CARRY4 whitebox	2019-05-27 23:09:06 -07:00