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Merge branch 'xaig' into xc7mux

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This commit is contained in:
Eddie Hung 2019-05-31 13:03:03 -07:00
commit eb08e71bd1
5 changed files with 99 additions and 15 deletions
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2
techlibs/ice40/cells_sim.v
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@ -149,7 +149,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
always @(posedge C)
Q <= D;
`else
always @* Q = D;
always @* Q <= D;
`endif
endmodule

1
techlibs/xilinx/synth_xilinx.cc
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@ -294,6 +294,7 @@ struct SynthXilinxPass : public ScriptPass
else
run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
run("clean");
// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming
if (!nosrl || help_mode)