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Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"

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This commit is contained in:
Eddie Hung 2019-06-12 08:49:15 -07:00
parent 4c9fde87d1
commit 1e838a8913
2 changed files with 14 additions and 6 deletions
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2
techlibs/xilinx/synth_xilinx.cc
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@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_luts")) {
if (abc == "abc9")
run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : ""));
else if (help_mode)
run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
else