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Consistent with xilinx

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This commit is contained in:
Eddie Hung 2019-06-03 09:23:43 -07:00
parent 2228cef62f
commit 9f44a71715
3 changed files with 4 additions and 4 deletions
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2
techlibs/ice40/abc_hx.box
View file

@ -4,7 +4,7 @@
# Inputs: C D
# Outputs: Q
SB_DFF 1 1 2 1
SB_DFF 1 0 2 1
- -
# Inputs: C D E

2
techlibs/ice40/cells_sim.v
View file

@ -145,7 +145,7 @@ endmodule
(* abc_box_id = 1, abc_flop, lib_whitebox *)
module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
`ifndef ABC_MODEL
`ifndef _ABC
always @(posedge C)
Q <= D;
`else

4
techlibs/ice40/synth_ice40.cc
View file

@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@ -334,7 +334,7 @@ struct SynthIce40Pass : public ScriptPass
if (abc == "abc9")
run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
else
run(abc + " -lut 4", "(skip if -noabc)");
run(abc + " -dress -lut 4", "(skip if -noabc)");
}
run("clean");
if (relut || help_mode) {