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Code Activity
14368 commits 122 branches 59 tags 72 MiB
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1555 commits

Author SHA1 Message Date
Eddie Hung
ea6ffea2cd Fix clk_pol for FD*_1 2019-07-10 20:10:20 -07:00
Eddie Hung
e603d719d6 Fix spacing 2019-07-10 19:04:22 -07:00
Eddie Hung
4a995c5d80 Change how to specify flops to ABC again 2019-07-10 17:54:56 -07:00
Eddie Hung
a092c48f03 Use split_tokens() 2019-07-10 17:34:51 -07:00
Eddie Hung
052060f109 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-10 16:05:41 -07:00
Clifford Wolf
6dd33be7ce
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position 
write_verilog: fix placement of case attributes
 2019-07-09 22:51:25 +02:00
whitequark
37bb6b5e96 write_verilog: fix placement of case attributes. NFC. 2019-07-09 19:14:03 +00:00
whitequark
6a29e1f5b7 write_verilog: write RTLIL::Sa aka - as Verilog ?. 
Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
 2019-07-09 18:35:49 +00:00
Eddie Hung
00d8a9dce2
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore 
Rename __builtin_bswap32 -> bswap32
 2019-07-09 10:22:57 -07:00
Eddie Hung
5a0f2e43c7 Rename __builtin_bswap32 -> bswap32 2019-07-09 09:35:09 -07:00
whitequark
628437b01c verilog_backend: dump attributes on SwitchRule. 
This appears to be an omission.
 2019-07-08 15:11:29 +00:00
whitequark
55c1f40277 verilog_backend: dump attributes on CaseRule, as comments. 
Attributes are not permitted in that position by Verilog grammar.
 2019-07-08 12:48:50 +00:00
whitequark
93bc5affd3 Allow attributes on individual switch cases in RTLIL. 
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
 2019-07-08 11:34:58 +00:00
Eddie Hung
10524064e9 write_xaiger to treat unknown cell connections as keep-s 2019-07-02 19:14:30 -07:00
Eddie Hung
69f4c039ce Safe side: all flops have different mergeability class 2019-07-02 12:21:03 -07:00
Eddie Hung
a31e17182d Refactor and cope with new abc_flop format 2019-07-01 11:50:34 -07:00
Eddie Hung
699d8e3939 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-01 10:44:42 -07:00
Eddie Hung
38d8806bd7 Add generic __builtin_bswap32 function 2019-06-28 09:59:47 -07:00
Eddie Hung
524af21317 Also fix write_aiger for UB 2019-06-28 09:55:07 -07:00
Eddie Hung
36e2eb06bb Fix more potential for undefined behaviour due to container invalidation 2019-06-28 09:51:43 -07:00
Eddie Hung
9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung
6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung
080a5ca536 Improve debugging message for comb loops 2019-06-26 20:02:38 -07:00
Eddie Hung
cec2292b0b Merge remote-tracking branch 'origin/master' into xaig 2019-06-24 20:01:43 -07:00
Eddie Hung
7903ebe3e0 Carry in/out box ordering now move to end, not swap with end 2019-06-22 14:18:42 -07:00
Eddie Hung
1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung
fddb027cab Replace assert with error message 2019-06-21 17:18:04 -07:00
Eddie Hung
7074ec9cd5 Add log_push()/log_pop() inside write_xaiger 2019-06-21 17:17:29 -07:00
Eddie Hung
65c1199acd One more workaround for gcc-4.8 2019-06-21 14:36:24 -07:00
Eddie Hung
bd7ec673dd No point logging constant bit 2019-06-21 14:31:09 -07:00
Eddie Hung
70c93ea0c4 Move comment 2019-06-21 14:31:09 -07:00
Miodrag Milanovic
fde90f7f8e Fix json formatting 2019-06-21 20:01:40 +02:00
Miodrag Milanovic
50e7221077 Add upto and offset to JSON ports 2019-06-21 19:47:25 +02:00
Clifford Wolf
f15def325c Added JSON upto and offset 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 15:22:17 +02:00
Eddie Hung
6a336ca23e Fix spacing 2019-06-20 22:30:20 -07:00
Eddie Hung
e21f01d938 Refactor bit2aig for less lookups 2019-06-20 22:10:43 -07:00
Eddie Hung
4422b7311b Fix gcc invalidation behaviour for write_aiger 2019-06-20 22:10:43 -07:00
Eddie Hung
32f8014e12 Fix gcc error, due to dict invalidation during recursion 2019-06-20 22:10:43 -07:00
Eddie Hung
c4ea6fff65 Fix gcc invalidation behaviour for write_aiger 2019-06-20 21:56:47 -07:00
Eddie Hung
8e56cfb6bb write_xaiger to flatten 1'bx/1'bz to 1'b0 again 2019-06-20 19:41:27 -07:00
Eddie Hung
ad36eb24c0 Fix different abc9 test 2019-06-20 19:41:27 -07:00
Eddie Hung
9faeba7a66 Fix broken abc9.v test due to inout being 1'bx 2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung
4e5836a5fb Handle COs driven by 1'bx 2019-06-20 17:38:04 -07:00
Eddie Hung
f2d541962e write_xaiger to skip POs driven by 1'bx 2019-06-20 17:37:54 -07:00
Ben Widawsky
4a18e19fb8 Support filename rewrite in backends 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:39:52 -07:00
Clifford Wolf
c23bbc4291 Add timescale and generated-by header to yosys-smtbmc MkVcd 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-16 23:12:03 +02:00
Eddie Hung
0c59bc0b75 Cleanup 2019-06-16 10:42:00 -07:00
Eddie Hung
fb90d8c18c Cleanup 2019-06-16 09:34:26 -07:00
Eddie Hung
6852c83bbe Cleanup write_xaiger 2019-06-15 22:50:15 -07:00