mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-12 12:08:19 +00:00
Code Activity

Cleanup

Browse source
This commit is contained in:
Eddie Hung 2019-06-16 10:42:00 -07:00
parent 59dcfcc919
commit 0c59bc0b75
5 changed files with 58 additions and 72 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

67
backends/aiger/xaiger.cc
View file

@ -233,49 +233,40 @@ struct XAigerWriter
}
RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr;
bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
if (inst_flop) {
toposort.node(cell->name);
if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
abc_box_seen = true;
for (const auto &c : cell->connections()) {
auto is_input = cell->input(c.first);
auto is_output = cell->output(c.first);
log_assert(is_input || is_output);
RTLIL::Wire* port = inst_module->wire(c.first);
if (is_input && port->attributes.count("\\abc_flop_d")) {
SigBit d = c.second;
SigBit I = sigmap(d);
if (I != d)
alias_map[I] = d;
unused_bits.erase(d);
}
if (is_output && port->attributes.count("\\abc_flop_q")) {
SigBit q = c.second;
SigBit O = sigmap(q);
if (O != q)
alias_map[O] = q;
undriven_bits.erase(O);
ff_bits.emplace_back(q);
toposort.node(cell->name);
auto abc_flop_d = inst_module->attributes.at("\\abc_flop_d", RTLIL::Const());
if (abc_flop_d.size() == 0) {
for (const auto &conn : cell->connections()) {
if (cell->input(conn.first)) {
// Ignore inout for the sake of topographical ordering
if (cell->output(conn.first)) continue;
for (auto bit : sigmap(conn.second))
bit_users[bit].insert(cell->name);
}
if (cell->output(conn.first))
for (auto bit : sigmap(conn.second))
bit_drivers[bit].insert(cell->name);
}
}
log_assert(inst_module->attributes.count("\\abc_box_id"));
abc_box_seen = true;
}
else if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
abc_box_seen = true;
else {
auto abc_flop_q = inst_module->attributes.at("\\abc_flop_q");
toposort.node(cell->name);
for (const auto &conn : cell->connections()) {
if (cell->input(conn.first)) {
// Ignore inout for the sake of topographical ordering
if (cell->output(conn.first)) continue;
for (auto bit : sigmap(conn.second))
bit_users[bit].insert(cell->name);
}
SigBit d = cell->getPort(RTLIL::escape_id(abc_flop_d.decode_string()));
SigBit I = sigmap(d);
if (I != d)
alias_map[I] = d;
unused_bits.erase(d);
if (cell->output(conn.first))
for (auto bit : sigmap(conn.second))
bit_drivers[bit].insert(cell->name);
SigBit q = cell->getPort(RTLIL::escape_id(abc_flop_q.decode_string()));
SigBit O = sigmap(q);
if (O != q)
alias_map[O] = q;
undriven_bits.erase(O);
ff_bits.emplace_back(q);
}
}
else {

41
frontends/aiger/aigerparse.cc
View file

@ -737,11 +737,13 @@ void AigerReader::post_process()
log_assert(box_module);
RTLIL::Module* flop_module = nullptr;
if (box_module->attributes.count("\\abc_flop")) {
auto flop_module_name = box_module->attributes.at("\\abc_flop", RTLIL::Const());
RTLIL::IdString flop_past_q;
if (flop_module_name.size() > 0) {
log_assert(flop_count < flopNum);
log_assert(box_module->name.begins_with("$__ABC_"));
flop_module = design->module("\\" + box_module->name.substr(7));
flop_module = design->module(RTLIL::escape_id(flop_module_name.decode_string()));
log_assert(flop_module);
flop_past_q = box_module->attributes.at("\\abc_flop_past_q").decode_string();
}
else if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
@ -778,8 +780,6 @@ void AigerReader::post_process()
}
}
RTLIL::Wire *d = nullptr;
RTLIL::Wire *q = nullptr;
// NB: Assume box_module->ports are sorted alphabetically
// (as RTLIL::Module::fixup_ports() would do)
for (auto port_name : box_module->ports) {
@ -789,14 +789,6 @@ void AigerReader::post_process()
for (int i = 0; i < GetSize(port); i++) {
RTLIL::Wire* wire = nullptr;
if (port->port_input) {
if (flop_module && port->attributes.count("\\abc_flop_d")) {
log_assert(!d);
d = outputs[outputs.size() - flopNum + flop_count];
log_assert(d);
log_assert(d->port_output);
d->port_output = false;
}
log_assert(co_count < outputs.size());
wire = outputs[co_count++];
log_assert(wire);
@ -804,14 +796,6 @@ void AigerReader::post_process()
wire->port_output = false;
}
if (port->port_output) {
if (flop_module && port->attributes.count("\\abc_flop_q")) {
log_assert(!q);
q = inputs[piNum - flopNum + flop_count];
log_assert(q);
log_assert(q->port_input);
q->port_input = false;
}
log_assert((piNum + ci_count) < inputs.size());
wire = inputs[piNum + ci_count++];
log_assert(wire);
@ -820,13 +804,24 @@ void AigerReader::post_process()
}
rhs.append(wire);
}
if (!flop_module || !port->attributes.count("\\abc_discard"))
if (!flop_module || port_name != flop_past_q)
cell->setPort(port_name, rhs);
}
if (flop_module) {
RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count];
log_assert(d);
log_assert(d->port_output);
d->port_output = false;
RTLIL::Wire *q = inputs[piNum - flopNum + flop_count];
log_assert(q);
log_assert(q->port_input);
q->port_input = false;
flop_count++;
cell->type = flop_module->name;
//module->addFfGate(NEW_ID, d1 q);
module->connect(q, d);
}
}

6
techlibs/xilinx/abc_ff.v
View file

@ -23,11 +23,11 @@
module \$__ABC_FF_ (input C, D, output Q);
endmodule
(* abc_box_id = 6, lib_whitebox, abc_flop *)
module \$__ABC_FDRE ((* abc_flop_q *) output Q, input C, CE, (* abc_flop_d *) input D, (* abc_flop_q_past, abc_discard *) input Q_past, input R);
(* abc_box_id = 6, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : Q_past);
assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
endmodule

4
techlibs/xilinx/abc_xc7.box
View file

@ -41,8 +41,8 @@ RAM128X1D 5 0 17 2
- - - - - - - - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - - - - - - - - - -
# Inputs: C CE D Q_past R
# Outputs: Q_next
# Inputs: C CE D R \$pastQ
# Outputs: Q
FDRE 6 1 5 1
- - - - -

12
techlibs/xilinx/ff_map.v
View file

@ -27,9 +27,9 @@ module \$_DFF_P_ (input D, C, output Q);
`ifndef _ABC
FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
`else
wire Q_next;
\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
\$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
wire \$nextQ ;
\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(1'b1), .R(1'b0));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
`endif
endmodule
@ -38,9 +38,9 @@ module \$_DFFE_PP_ (input D, C, E, output Q);
`ifndef _ABC
FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
`else
wire Q_next;
\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(E), .R(1'b0));
\$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
wire \$nextQ ;
\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(E), .R(1'b0));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
`endif
endmodule