mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 01:54:10 +00:00
Code Activity

verilog_backend: dump attributes on SwitchRule.

Browse source 
This appears to be an omission.
This commit is contained in:
whitequark 2019-07-08 15:11:29 +00:00
parent 48655dfb8b
commit 628437b01c
1 changed files with 1 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
backends/verilog/verilog_backend.cc
View file

@ -1494,6 +1494,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
return;
}
dump_attributes(f, indent, sw->attributes);
f << stringf("%s" "casez (", indent.c_str());
dump_sigspec(f, sw->signal);
f << stringf(")\n");