whitequark 6a29e1f5b7 write_verilog: write RTLIL::Sa aka - as Verilog ?. ... Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.		2019-07-09 18:35:49 +00:00
..
aiger	write_xaiger to treat unknown cell connections as keep-s	2019-07-02 19:14:30 -07:00
blif	Fix handling of offset and upto module ports in write_blif, fixes #1040	2019-05-25 17:45:14 +02:00
btor	Merge origin/master	2019-06-27 11:20:15 -07:00
edif	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
firrtl	Fix static shift operands, neg result type, minor formatting	2019-05-21 13:04:56 -07:00
ilang	Allow attributes on individual switch cases in RTLIL.	2019-07-08 11:34:58 +00:00
intersynth	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
json	Fix json formatting	2019-06-21 20:01:40 +02:00
protobuf	Support filename rewrite in backends	2019-06-18 14:39:52 -07:00
simplec	Fix typographical and grammatical errors and inconsistencies.	2019-01-02 13:12:17 +00:00
smt2	Merge origin/master	2019-06-27 11:20:15 -07:00
smv	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
spice	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
table	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
verilog	write_verilog: write RTLIL::Sa aka - as Verilog ?.	2019-07-09 18:35:49 +00:00