mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
Merge remote-tracking branch 'origin/master' into xaig_dff
This commit is contained in:
Eddie Hung
commit
699d8e3939
92 changed files with 3035 additions and 853 deletions
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@ -70,34 +70,35 @@ struct AigerWriter
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int bit2aig(SigBit bit)
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{
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if (aig_map.count(bit) == 0)
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{
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aig_map[bit] = -1;
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if (initstate_bits.count(bit)) {
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log_assert(initstate_ff > 0);
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aig_map[bit] = initstate_ff;
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} else
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if (not_map.count(bit)) {
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int a = bit2aig(not_map.at(bit)) ^ 1;
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aig_map[bit] = a;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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aig_map[bit] = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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aig_map[bit] = bit2aig(alias_map.at(bit));
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}
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if (bit == State::Sx || bit == State::Sz)
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log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
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auto it = aig_map.find(bit);
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if (it != aig_map.end()) {
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log_assert(it->second >= 0);
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return it->second;
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}
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log_assert(aig_map.at(bit) >= 0);
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return aig_map.at(bit);
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// NB: Cannot use iterator returned from aig_map.insert()
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// since this function is called recursively
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int a = -1;
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if (not_map.count(bit)) {
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a = bit2aig(not_map.at(bit)) ^ 1;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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a = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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a = bit2aig(alias_map.at(bit));
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}
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if (bit == State::Sx || bit == State::Sz)
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log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
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log_assert(a >= 0);
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aig_map[bit] = a;
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return a;
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}
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AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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@ -776,6 +777,7 @@ struct AigerBackend : public Backend {
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writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
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if (!map_filename.empty()) {
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rewrite_filename(filename);
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std::ofstream mapf;
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mapf.open(map_filename.c_str(), std::ofstream::trunc);
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if (mapf.fail())
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@ -25,6 +25,21 @@
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#elif defined(__APPLE__)
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#include <libkern/OSByteOrder.h>
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#define __builtin_bswap32 OSSwapInt32
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#elif !defined(__GNUC__)
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#include <cstdint>
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inline uint32_t __builtin_bswap32(uint32_t x)
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{
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// https://stackoverflow.com/a/27796212
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register uint32_t value = number_to_be_reversed;
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uint8_t lolo = (value >> 0) & 0xFF;
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uint8_t lohi = (value >> 8) & 0xFF;
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uint8_t hilo = (value >> 16) & 0xFF;
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uint8_t hihi = (value >> 24) & 0xFF;
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return (hihi << 24)
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| (hilo << 16)
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| (lohi << 8)
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| (lolo << 0);
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}
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#endif
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#include "kernel/yosys.h"
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@ -79,6 +94,7 @@ struct XAigerWriter
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dict<SigBit, int> ordered_latches;
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vector<Cell*> box_list;
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bool omode = false;
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//dict<SigBit, int> init_inputs;
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//int initstate_ff = 0;
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@ -92,30 +108,37 @@ struct XAigerWriter
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int bit2aig(SigBit bit)
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{
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if (aig_map.count(bit) == 0)
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{
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aig_map[bit] = -1;
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if (not_map.count(bit)) {
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int a = bit2aig(not_map.at(bit)) ^ 1;
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aig_map[bit] = a;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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aig_map[bit] = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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aig_map[bit] = bit2aig(alias_map.at(bit));
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}
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if (bit == State::Sx || bit == State::Sz)
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log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
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auto it = aig_map.find(bit);
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if (it != aig_map.end()) {
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log_assert(it->second >= 0);
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return it->second;
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}
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log_assert(aig_map.at(bit) >= 0);
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return aig_map.at(bit);
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// NB: Cannot use iterator returned from aig_map.insert()
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// since this function is called recursively
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int a = -1;
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if (not_map.count(bit)) {
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a = bit2aig(not_map.at(bit)) ^ 1;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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a = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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a = bit2aig(alias_map.at(bit));
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}
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if (bit == State::Sx || bit == State::Sz) {
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log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
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a = aig_map.at(State::S0);
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}
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log_assert(a >= 0);
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aig_map[bit] = a;
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return a;
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}
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XAigerWriter(Module *module, bool zinit_mode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
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@ -167,9 +190,13 @@ struct XAigerWriter
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}
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if (wire->port_output || keep) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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if (bit != RTLIL::Sx) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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}
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else
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log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
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}
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}
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}
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@ -274,7 +301,8 @@ struct XAigerWriter
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if (c.second.is_fully_const()) continue;
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auto is_input = cell->input(c.first);
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auto is_output = cell->output(c.first);
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log_assert(is_input || is_output);
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if (!is_input && !is_output)
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log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
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if (is_input) {
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for (auto b : c.second.bits()) {
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@ -313,8 +341,6 @@ struct XAigerWriter
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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pool<RTLIL::Module*> abc_carry_modules;
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#if 0
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toposort.analyze_loops = true;
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#endif
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@ -322,53 +348,63 @@ struct XAigerWriter
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#if 0
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d", i++);
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for (auto cell : it)
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log(" %s", log_id(cell));
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log("\n");
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log(" loop %d\n", i++);
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for (auto cell_name : it) {
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auto cell = module->cell(cell_name);
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log_assert(cell);
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log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
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}
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}
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#endif
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log_assert(no_loops);
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pool<IdString> seen_boxes;
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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log_assert(cell);
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RTLIL::Module* box_module = module->design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc_box_id"))
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continue;
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if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
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RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
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RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
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for (const auto &port_name : box_module->ports) {
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RTLIL::Wire* w = box_module->wire(port_name);
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log_assert(w);
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if (w->port_input) {
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if (w->attributes.count("\\abc_carry_in")) {
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log_assert(!carry_in);
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carry_in = w;
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}
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log_assert(!last_in || last_in->port_id < w->port_id);
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last_in = w;
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}
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if (w->port_output) {
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if (w->attributes.count("\\abc_carry_out")) {
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log_assert(!carry_out);
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carry_out = w;
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}
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log_assert(!last_out || last_out->port_id < w->port_id);
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last_out = w;
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}
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}
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if (seen_boxes.insert(cell->type).second) {
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auto it = box_module->attributes.find("\\abc_carry");
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if (it != box_module->attributes.end()) {
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RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
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auto carry_in_out = it->second.decode_string();
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auto pos = carry_in_out.find(',');
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if (pos == std::string::npos)
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log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
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auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
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carry_in = box_module->wire(carry_in_name);
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if (!carry_in || !carry_in->port_input)
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log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
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if (carry_in) {
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log_assert(last_in);
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std::swap(box_module->ports[carry_in->port_id-1], box_module->ports[last_in->port_id-1]);
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std::swap(carry_in->port_id, last_in->port_id);
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}
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if (carry_out) {
|
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log_assert(last_out);
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std::swap(box_module->ports[carry_out->port_id-1], box_module->ports[last_out->port_id-1]);
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std::swap(carry_out->port_id, last_out->port_id);
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auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
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carry_out = box_module->wire(carry_out_name);
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if (!carry_out || !carry_out->port_output)
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log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
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auto &ports = box_module->ports;
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for (auto jt = ports.begin(); jt != ports.end(); ) {
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RTLIL::Wire* w = box_module->wire(*jt);
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log_assert(w);
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if (w == carry_in || w == carry_out) {
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jt = ports.erase(jt);
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continue;
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}
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if (w->port_id > carry_in->port_id)
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--w->port_id;
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if (w->port_id > carry_out->port_id)
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--w->port_id;
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log_assert(w->port_input || w->port_output);
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log_assert(ports[w->port_id-1] == w->name);
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++jt;
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}
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ports.push_back(carry_in->name);
|
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carry_in->port_id = ports.size();
|
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ports.push_back(carry_out->name);
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carry_out->port_id = ports.size();
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}
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}
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|
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|
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@ -393,10 +429,16 @@ struct XAigerWriter
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}
|
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int offset = 0;
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for (const auto &b : rhs.bits()) {
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for (auto b : rhs.bits()) {
|
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SigBit I = sigmap(b);
|
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if (I != b)
|
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alias_map[b] = I;
|
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if (b == RTLIL::Sx)
|
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b = RTLIL::S0;
|
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else if (I != b) {
|
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if (I == RTLIL::Sx)
|
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alias_map[b] = RTLIL::S0;
|
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else
|
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alias_map[b] = I;
|
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}
|
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co_bits.emplace_back(b, cell, port_name, offset++, 0);
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unused_bits.erase(b);
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}
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|
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@ -437,27 +479,33 @@ struct XAigerWriter
|
|||
}
|
||||
|
||||
for (auto bit : input_bits) {
|
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if (!output_bits.count(bit))
|
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continue;
|
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RTLIL::Wire *wire = bit.wire;
|
||||
// If encountering an inout port, or a keep-ed wire, then create a new wire
|
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// with $inout.out suffix, make it a PO driven by the existing inout, and
|
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// inherit existing inout's drivers
|
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if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
|
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|| wire->attributes.count("\\keep")) {
|
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log_assert(input_bits.count(bit) && output_bits.count(bit));
|
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RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
|
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RTLIL::Wire *new_wire = module->wire(wire_name);
|
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if (!new_wire)
|
||||
new_wire = module->addWire(wire_name, GetSize(wire));
|
||||
SigBit new_bit(new_wire, bit.offset);
|
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module->connect(new_bit, bit);
|
||||
if (not_map.count(bit))
|
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not_map[new_bit] = not_map.at(bit);
|
||||
else if (and_map.count(bit))
|
||||
and_map[new_bit] = and_map.at(bit);
|
||||
else if (alias_map.count(bit))
|
||||
alias_map[new_bit] = alias_map.at(bit);
|
||||
if (not_map.count(bit)) {
|
||||
auto a = not_map.at(bit);
|
||||
not_map[new_bit] = a;
|
||||
}
|
||||
else if (and_map.count(bit)) {
|
||||
auto a = and_map.at(bit);
|
||||
and_map[new_bit] = a;
|
||||
}
|
||||
else if (alias_map.count(bit)) {
|
||||
auto a = alias_map.at(bit);
|
||||
alias_map[new_bit] = a;
|
||||
}
|
||||
else
|
||||
//log_abort();
|
||||
alias_map[new_bit] = bit;
|
||||
output_bits.erase(bit);
|
||||
output_bits.insert(new_bit);
|
||||
|
|
@ -590,6 +638,12 @@ struct XAigerWriter
|
|||
aig_o++;
|
||||
aig_outputs.push_back(ff_aig_map.at(bit));
|
||||
}
|
||||
|
||||
if (output_bits.empty()) {
|
||||
aig_o++;
|
||||
aig_outputs.push_back(0);
|
||||
omode = true;
|
||||
}
|
||||
}
|
||||
|
||||
void write_aiger(std::ostream &f, bool ascii_mode)
|
||||
|
|
@ -796,6 +850,8 @@ struct XAigerWriter
|
|||
f.write(buffer_str.data(), buffer_str.size());
|
||||
|
||||
if (holes_module) {
|
||||
log_push();
|
||||
|
||||
// NB: fixup_ports() will sort ports by name
|
||||
//holes_module->fixup_ports();
|
||||
holes_module->check();
|
||||
|
|
@ -832,6 +888,8 @@ struct XAigerWriter
|
|||
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
|
||||
f.write(buffer_str.data(), buffer_str.size());
|
||||
holes_module->design->remove(holes_module);
|
||||
|
||||
log_pop();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -915,6 +973,8 @@ struct XAigerWriter
|
|||
for (auto &it : output_lines)
|
||||
f << it.second;
|
||||
log_assert(output_lines.size() == output_bits.size());
|
||||
if (omode && output_bits.empty())
|
||||
f << "output " << output_lines.size() << " 0 $__dummy__\n";
|
||||
|
||||
latch_lines.sort();
|
||||
for (auto &it : latch_lines)
|
||||
|
|
|
|||
|
|
@ -17,6 +17,11 @@
|
|||
*
|
||||
*/
|
||||
|
||||
// [[CITE]] Btor2 , BtorMC and Boolector 3.0
|
||||
// Aina Niemetz, Mathias Preiner, Clifford Wolf, Armin Biere
|
||||
// Computer Aided Verification - 30th International Conference, CAV 2018
|
||||
// https://cs.stanford.edu/people/niemetz/publication/2018/niemetzpreinerwolfbiere-cav18/
|
||||
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/sigtools.h"
|
||||
|
|
@ -875,9 +880,28 @@ struct BtorWorker
|
|||
else
|
||||
{
|
||||
if (bit_cell.count(bit) == 0)
|
||||
log_error("No driver for signal bit %s.\n", log_signal(bit));
|
||||
export_cell(bit_cell.at(bit));
|
||||
log_assert(bit_nid.count(bit));
|
||||
{
|
||||
SigSpec s = bit;
|
||||
|
||||
while (i+GetSize(s) < GetSize(sig) && sig[i+GetSize(s)].wire != nullptr &&
|
||||
bit_cell.count(sig[i+GetSize(s)]) == 0)
|
||||
s.append(sig[i+GetSize(s)]);
|
||||
|
||||
log_warning("No driver for signal %s.\n", log_signal(s));
|
||||
|
||||
int sid = get_bv_sid(GetSize(s));
|
||||
int nid = next_nid++;
|
||||
btorf("%d input %d %s\n", nid, sid);
|
||||
nid_width[nid] = GetSize(s);
|
||||
|
||||
i += GetSize(s)-1;
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
export_cell(bit_cell.at(bit));
|
||||
log_assert(bit_nid.count(bit));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -483,6 +483,7 @@ struct DumpPass : public Pass {
|
|||
std::stringstream buf;
|
||||
|
||||
if (!filename.empty()) {
|
||||
rewrite_filename(filename);
|
||||
std::ofstream *ff = new std::ofstream;
|
||||
ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc);
|
||||
if (ff->fail()) {
|
||||
|
|
|
|||
|
|
@ -126,6 +126,10 @@ struct JsonWriter
|
|||
f << stringf("%s\n", first ? "" : ",");
|
||||
f << stringf(" %s: {\n", get_name(n).c_str());
|
||||
f << stringf(" \"direction\": \"%s\",\n", w->port_input ? w->port_output ? "inout" : "input" : "output");
|
||||
if (w->start_offset)
|
||||
f << stringf(" \"offset\": %d,\n", w->start_offset);
|
||||
if (w->upto)
|
||||
f << stringf(" \"upto\": 1,\n");
|
||||
f << stringf(" \"bits\": %s\n", get_bits(w).c_str());
|
||||
f << stringf(" }");
|
||||
first = false;
|
||||
|
|
@ -189,6 +193,10 @@ struct JsonWriter
|
|||
f << stringf(" %s: {\n", get_name(w->name).c_str());
|
||||
f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
|
||||
f << stringf(" \"bits\": %s,\n", get_bits(w).c_str());
|
||||
if (w->start_offset)
|
||||
f << stringf(" \"offset\": %d,\n", w->start_offset);
|
||||
if (w->upto)
|
||||
f << stringf(" \"upto\": 1,\n");
|
||||
f << stringf(" \"attributes\": {");
|
||||
write_parameters(w->attributes);
|
||||
f << stringf("\n }\n");
|
||||
|
|
@ -525,6 +533,7 @@ struct JsonPass : public Pass {
|
|||
std::stringstream buf;
|
||||
|
||||
if (!filename.empty()) {
|
||||
rewrite_filename(filename);
|
||||
std::ofstream *ff = new std::ofstream;
|
||||
ff->open(filename.c_str(), std::ofstream::trunc);
|
||||
if (ff->fail()) {
|
||||
|
|
|
|||
|
|
@ -336,6 +336,7 @@ struct ProtobufPass : public Pass {
|
|||
std::stringstream buf;
|
||||
|
||||
if (!filename.empty()) {
|
||||
rewrite_filename(filename);
|
||||
std::ofstream *ff = new std::ofstream;
|
||||
ff->open(filename.c_str(), std::ofstream::trunc);
|
||||
if (ff->fail()) {
|
||||
|
|
|
|||
|
|
@ -1023,6 +1023,8 @@ class MkVcd:
|
|||
assert t >= self.t
|
||||
if t != self.t:
|
||||
if self.t == -1:
|
||||
print("$version Generated by Yosys-SMTBMC $end", file=self.f)
|
||||
print("$timescale 1ns $end", file=self.f)
|
||||
print("$var integer 32 t smt_step $end", file=self.f)
|
||||
print("$var event 1 ! smt_clock $end", file=self.f)
|
||||
|
||||
|
|
@ -1041,7 +1043,10 @@ class MkVcd:
|
|||
scope = scope[:-1]
|
||||
|
||||
while uipath[:-1] != scope:
|
||||
print("$scope module %s $end" % uipath[len(scope)], file=self.f)
|
||||
scopename = uipath[len(scope)]
|
||||
if scopename.startswith("$"):
|
||||
scopename = "\\" + scopename
|
||||
print("$scope module %s $end" % scopename, file=self.f)
|
||||
scope.append(uipath[len(scope)])
|
||||
|
||||
if path in self.clocks and self.clocks[path][1] == "event":
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue